Stratix® 10 General Purpose I/O User Guide

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ID 683518
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 I/O Overview 2. Stratix® 10 I/O Architecture and Features 3. Stratix® 10 I/O Design Considerations 4. Stratix® 10 I/O Implementation Guides 5. GPIO Intel® FPGA IP Reference 6. Document Revision History for the Stratix® 10 General Purpose I/O User Guide
1. Stratix® 10 I/O Overview x
1.1. Stratix® 10 I/O and Differential I/O Buffers 1.2. Stratix® 10 I/O Migration Support
2. Stratix® 10 I/O Architecture and Features x
2.1. I/O Standards and Voltage Levels in Stratix® 10 Devices 2.2. I/O Element Structure in Stratix® 10 Devices 2.3. Programmable IOE Features in Stratix® 10 Devices 2.4. On-Chip I/O Termination in Stratix® 10 Devices 2.5. External I/O Termination for Stratix® 10 Devices
2.1. I/O Standards and Voltage Levels in Stratix® 10 Devices x
2.1.1. Stratix® 10 I/O Standards Support 2.1.2. Stratix® 10 I/O Standards Voltage Support
2.2. I/O Element Structure in Stratix® 10 Devices x
2.2.1. I/O Bank Architecture in Stratix® 10 Devices 2.2.2. I/O Buffer and Registers in Stratix® 10 Devices
2.3. Programmable IOE Features in Stratix® 10 Devices x
2.3.1. Programmable Output Slew Rate Control 2.3.2. Programmable IOE Delay 2.3.3. Programmable Open-Drain Output 2.3.4. Programmable Bus Hold 2.3.5. Programmable Pull-Up Resistor 2.3.6. Programmable Pre-Emphasis 2.3.7. Programmable Differential Output Voltage 2.3.8. Programmable Current Strength
2.4. On-Chip I/O Termination in Stratix® 10 Devices x
2.4.1. RS OCT without Calibration in Stratix® 10 Devices 2.4.2. RS OCT with Calibration in Stratix® 10 Devices 2.4.3. RT OCT with Calibration in Stratix® 10 Devices 2.4.4. Dynamic OCT 2.4.5. Differential Input RD OCT 2.4.6. OCT Calibration Block in Stratix® 10 Devices
2.5. External I/O Termination for Stratix® 10 Devices x
2.5.1. Single-Ended I/O Termination 2.5.2. Differential I/O Termination for Stratix® 10 Devices
2.5.2. Differential I/O Termination for Stratix® 10 Devices x
2.5.2.1. Differential HSTL, SSTL, HSUL, and POD Termination 2.5.2.2. LVDS, RSDS, and Mini-LVDS Termination 2.5.2.3. LVPECL Termination
3. Stratix® 10 I/O Design Considerations x
3.1. Guideline: VREF Sources and VREF Pins 3.2. Guideline: Observe Device Absolute Maximum Rating for 3.0 V Interfacing 3.3. Guideline: Voltage-Referenced and Non-Voltage Referenced I/O Standards 3.4. Guideline: Do Not Drive I/O Pins During Power Sequencing 3.5. Guideline: Stratix® 10 I/O Buffer During Power Up, Configuration, and Power Down 3.6. Guideline: Maximum DC Current Restrictions 3.7. Guideline: Use Only One Voltage for All 3 V I/O Banks 3.8. Guideline: I/O Standards Limitation for Stratix® 10 TX 400 3.9. Guideline: I/O Standards Limitation for Stratix® 10 GX 400 and SX 400
4. Stratix® 10 I/O Implementation Guides x
4.1. GPIO Intel® FPGA IP 4.2. Verifying Resource Utilization and Design Performance 4.3. GPIO Intel® FPGA IP Timing 4.4. GPIO Intel® FPGA IP Design Examples 4.5. Verifying Pin Migration Compatibility 4.6. IP Migration to the GPIO IP Core
4.1. GPIO Intel® FPGA IP x
4.1.1. Release Information for GPIO Intel® FPGA IP 4.1.2. GPIO Intel® FPGA IP Data Paths 4.1.3. Register Packing
4.1.2. GPIO Intel® FPGA IP Data Paths x
4.1.2.1. Input Path 4.1.2.2. Output and Output Enable Paths
4.3. GPIO Intel® FPGA IP Timing x
4.3.1. Timing Components 4.3.2. Delay Elements 4.3.3. Timing Analysis 4.3.4. Timing Closure Guidelines
4.3.3. Timing Analysis x
4.3.3.1. Single Data Rate Input Register 4.3.3.2. Full-Rate or Half-Rate DDIO Input Register 4.3.3.3. Single Data Rate Output Register 4.3.3.4. Full-Rate or Half-Rate DDIO Output Register
4.4. GPIO Intel® FPGA IP Design Examples x
4.4.1. GPIO Intel® FPGA IP Synthesizable Quartus® Prime Design Example 4.4.2. GPIO Intel® FPGA IP Simulation Design Example
4.6. IP Migration to the GPIO IP Core x
4.6.1. Migrating Your ALTDDIO_IN, ALTDDIO_OUT, ALTDDIO_BIDIR, and ALTIOBUF IP Cores 4.6.2. Guideline: Swap datain_h and datain_l Ports in Migrated IP
5. GPIO Intel® FPGA IP Reference x
5.1. GPIO Intel® FPGA IP Parameter Settings 5.2. GPIO Intel® FPGA IP Interface Signals
5.2. GPIO Intel® FPGA IP Interface Signals x
5.2.1. Shared Signals 5.2.2. Data Bit-Order for Data Interface 5.2.3. Data Interface Signals and Corresponding Clocks
1. Stratix® 10 I/O Overview
2. Stratix® 10 I/O Architecture and Features
3. Stratix® 10 I/O Design Considerations
4. Stratix® 10 I/O Implementation Guides
5. GPIO Intel® FPGA IP Reference
6. Document Revision History for the Stratix® 10 General Purpose I/O User Guide

2.2. I/O Element Structure in Stratix® 10 Devices

The I/O elements (IOEs) in Stratix® 10 devices contain a bidirectional I/O buffer and I/O registers to support a complete embedded bidirectional single data rate (SDR) or double data rate (DDR) transfer.

The IOEs are located in I/O columns within the core fabric of the Stratix® 10 device.

Stratix® 10 SX devices also have IOEs for the HPS.

The GPIO IOE register consists of the DDR register, the half rate register, and the transmitter delay chains for input, output, and output enable (OE) paths:

  • You can take data from the combinatorial path or the registered path.
  • Only the core clock clocks the data.
  • The half rate clock routed from the core clocks the half rate register.
  • The full rate clock from the core clocks the full rate register.

Section Content
I/O Bank Architecture in Stratix 10 Devices
I/O Buffer and Registers in Stratix 10 Devices

Level Two Title