R-Tile Avalon® Streaming FPGA IP for PCI Express* User Guide
ID
683501
Date
8/11/2025
Public
1. About the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express
2. IP Architecture and Functional Description
3. Advanced Features
4. Interfaces
5. Parameters
6. Troubleshooting/Debugging
7. R-Tile Avalon® Streaming FPGA IP for PCI Express* User Guide Archives
8. Document Revision History for the R-Tile Avalon® Streaming FPGA IP for PCI Express* User Guide
A. Configuration Space Registers
B. Root Port Enumeration
C. Implementation of Address Translation Services (ATS) in Endpoint Mode
D. Packets Forwarded to the User Application in TL Bypass Mode
E. Margin Masks for the R-Tile Avalon Streaming FPGA IP for PCI Express
F. Using the Avery BFM for R-Tile PCI Express Gen5 Simulations
3.2.2.5.1. VirtIO Common Configuration Capability Register (Address: 0x012)
3.2.2.5.2. VirtIO Common Configuration BAR Indicator Register (Address: 0x013)
3.2.2.5.3. VirtIO Common Configuration BAR Offset Register (Address: 0x014)
3.2.2.5.4. VirtIO Common Configuration Structure Length Register (Address 0x015)
3.2.2.5.5. VirtIO Notifications Capability Register (Address: 0x016)
3.2.2.5.6. VirtIO Notifications BAR Indicator Register (Address: 0x017)
3.2.2.5.7. VirtIO Notifications BAR Offset Register (Address: 0x018)
3.2.2.5.8. VirtIO Notifications Structure Length Register (Address: 0x019)
3.2.2.5.9. VirtIO Notifications Notify Off Multiplier Register (Address: 0x01A)
3.2.2.5.10. VirtIO ISR Status Capability Register (Address: 0x02F)
3.2.2.5.11. VirtIO ISR Status BAR Indicator Register (Address: 0x030)
3.2.2.5.12. VirtIO ISR Status BAR Offset Register (Address: 0x031)
3.2.2.5.13. VirtIO ISR Status Structure Length Register (Address: 0x032)
3.2.2.5.14. VirtIO Device Specific Capability Register (Address: 0x033)
3.2.2.5.15. VirtIO Device Specific BAR Indicator Register (Address: 0x034)
3.2.2.5.16. VirtIO Device Specific BAR Offset Register (Address 0x035)
3.2.2.5.17. VirtIO Device Specific Structure Length Register (Address: 0x036)
3.2.2.5.18. VirtIO PCI Configuration Access Capability Register (Address: 0x037)
3.2.2.5.19. VirtIO PCI Configuration Access BAR Indicator Register (Address: 0x038)
3.2.2.5.20. VirtIO PCI Configuration Access BAR Offset Register (Address: 0x039)
3.2.2.5.21. VirtIO PCI Configuration Access Structure Length Register (Address: 0x03A)
3.2.2.5.22. VirtIO PCI Configuration Access Data Register (Address: 0x03B)
4.3.1. Avalon® Streaming Interface
4.3.2. Precision Time Measurement (PTM) Interface (Endpoint Only)
4.3.3. Hot Plug Interface
4.3.4. Interrupt Interface
4.3.5. Hard IP Reconfiguration Interface
4.3.6. Error Interface
4.3.7. Completion Timeout Interface
4.3.8. Configuration Intercept Interface
4.3.9. Power Management Interface
4.3.10. Hard IP Status Interface
4.3.11. Page Request Services (PRS) Interface (Endpoint Only)
4.3.12. Function-Level Reset (FLR) Interface (Endpoint Only)
4.3.13. SR-IOV VF Error Flag Interface (Endpoint Only)
4.3.14. General Purpose VSEC Interface
5.2.3.1. Device Capabilities
5.2.3.2. VirtIO Parameters
5.2.3.3. Link Capabilities
5.2.3.4. Legacy Interrupt Pin Register
5.2.3.5. MSI Capabilities
5.2.3.6. MSI-X Capabilities
5.2.3.7. Slot Capabilities
5.2.3.8. Latency Tolerance Reporting (LTR)
5.2.3.9. Process Address Space ID (PASID)
5.2.3.10. Device Serial Number Capability
5.2.3.11. Page Request Service (PRS)
5.2.3.12. Access Control Service (ACS)
5.2.3.13. Power Management
5.2.3.14. Vendor Specific Extended Capability (VSEC) Registers
5.2.3.15. TLP Processing Hints (TPH)
5.2.3.16. Address Translation Services (ATS) Capabilities
5.2.3.17. Precision Time Measurement (PTM)
3.2.1.2.1. VF Error Flag Interface (for x16/x8 Cores Only)
The VFs, with no AER support, are required to generate Non-Fatal error messages. The IP does not generate any error message. It is up to the user application logic to generate appropriate messages when specific error conditions occur.
The R-Tile IP for PCIe makes necessary signals available to the user application logic to generate these messages. The Completion Timeout Interface (described in section Completion Timeout Interface) and the signals listed in the table below provide the necessary information to generate Non-Fatal error messages.
Signal Name | Direction | Description | Clock Domain | EP/RP/BP |
---|---|---|---|---|
X16: vf_err_poisonedwrreq_s0_o X8: vf_err_poisonedwrreq_s0/s1_o |
O | Indicates a Poisoned Write Request is received. | coreclkout_hip | EP |
X16: vf_err_poisonedcompl_s0_o X8: vf_err_poisonedcompl_s0/s1_o |
O | Indicates a Poisoned Completion is received. | coreclkout_hip | EP |
X16: vf_err_ur_posted_s0_o X8: vf_err_ur_posted_s0/s1_o |
O | Indicates the IP core received a Posted UR request. | coreclkout_hip | EP |
X16: vf_err_ca_postedreq_s0_o X8: vf_err_ca_postedreq_s0/s1_o |
O | Indicates the IP core received a Posted CA request. | coreclkout_hip | EP |
X16: vf_err_vf_num_s0_o[10:0] X8: vf_err_vf_num_s0/s1_o[10:0] |
O | Indicates the VF number for which the error is detected. | coreclkout_hip | EP |
X16: vf_err_func_num_s0_o[2:0] X8: vf_err_func_num_s0/s1_o[2:0] |
O | Indicates the physical function number associated with the VF that has the error. | coreclkout_hip | EP |
vf_err_overflow_o | O | Indicates a VF error FIFO overflow and a loss of an error report. The overflow can happen when coreclkout_hip is slower than the default value. If coreclkout_hip is running at the default frequency, the overflow will not happen. | coreclkout_hip | EP |
user_sent_vfnonfatalmsg_s0_i | I | Indicates the user application sent a non-fatal error message in response to an error detected. | coreclkout_hip | EP |
user_vfnonfatalmsg_vfnum_s0_i[10:0] | I | Indicates the VF number for which the error message was generated. This bus is valid when user_sent_vfnonfatalmsg_s0_i is high. | coreclkout_hip | EP |
user_vfnonfatalmsg_func_num_s0_i[2:0] | I | Indicates the PF number associated with the VF with the error. This bus is valid when user_sent_vfnonfatalmsg_s0_i is high. | coreclkout_hip | EP |