R-Tile Avalon® Streaming FPGA IP for PCI Express* User Guide

ID 683501
Date 8/11/2025
Public
Document Table of Contents

2.2.2.1. Single PERST

The following is an example where a single PERST# (pin_perst_n) is driven with independent refclk0 and refclk1. In this example, the add-in card (FPGA and Soc) is powered up first. The R-Tile refclk0 is fed by the on-board free-running oscillator and the refclk1 driven by the Host becomes stable later. Hence, the PERST# is connected to the Host.

Figure 5. Single PERST# Connection in Bifurcated 2x8 Mode
Consider the following guidelines for handling independent reset operations:
Input Port Used Sticky Bits Clearing Non-Sticky Bits Clearing PHY Lane Reset
pin_perst_n Yes (*) Yes Yes
Note: (*) The sticky bits are not cleared if all physical functions are enabled and the PME_en for each of the physical functions is enabled.