R-Tile Avalon® Streaming FPGA IP for PCI Express* User Guide
ID
683501
Date
8/11/2025
Public
1. About the R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express
2. IP Architecture and Functional Description
3. Advanced Features
4. Interfaces
5. Parameters
6. Troubleshooting/Debugging
7. R-Tile Avalon® Streaming FPGA IP for PCI Express* User Guide Archives
8. Document Revision History for the R-Tile Avalon® Streaming FPGA IP for PCI Express* User Guide
A. Configuration Space Registers
B. Root Port Enumeration
C. Implementation of Address Translation Services (ATS) in Endpoint Mode
D. Packets Forwarded to the User Application in TL Bypass Mode
E. Margin Masks for the R-Tile Avalon Streaming FPGA IP for PCI Express
F. Using the Avery BFM for R-Tile PCI Express Gen5 Simulations
3.2.2.5.1. VirtIO Common Configuration Capability Register (Address: 0x012)
3.2.2.5.2. VirtIO Common Configuration BAR Indicator Register (Address: 0x013)
3.2.2.5.3. VirtIO Common Configuration BAR Offset Register (Address: 0x014)
3.2.2.5.4. VirtIO Common Configuration Structure Length Register (Address 0x015)
3.2.2.5.5. VirtIO Notifications Capability Register (Address: 0x016)
3.2.2.5.6. VirtIO Notifications BAR Indicator Register (Address: 0x017)
3.2.2.5.7. VirtIO Notifications BAR Offset Register (Address: 0x018)
3.2.2.5.8. VirtIO Notifications Structure Length Register (Address: 0x019)
3.2.2.5.9. VirtIO Notifications Notify Off Multiplier Register (Address: 0x01A)
3.2.2.5.10. VirtIO ISR Status Capability Register (Address: 0x02F)
3.2.2.5.11. VirtIO ISR Status BAR Indicator Register (Address: 0x030)
3.2.2.5.12. VirtIO ISR Status BAR Offset Register (Address: 0x031)
3.2.2.5.13. VirtIO ISR Status Structure Length Register (Address: 0x032)
3.2.2.5.14. VirtIO Device Specific Capability Register (Address: 0x033)
3.2.2.5.15. VirtIO Device Specific BAR Indicator Register (Address: 0x034)
3.2.2.5.16. VirtIO Device Specific BAR Offset Register (Address 0x035)
3.2.2.5.17. VirtIO Device Specific Structure Length Register (Address: 0x036)
3.2.2.5.18. VirtIO PCI Configuration Access Capability Register (Address: 0x037)
3.2.2.5.19. VirtIO PCI Configuration Access BAR Indicator Register (Address: 0x038)
3.2.2.5.20. VirtIO PCI Configuration Access BAR Offset Register (Address: 0x039)
3.2.2.5.21. VirtIO PCI Configuration Access Structure Length Register (Address: 0x03A)
3.2.2.5.22. VirtIO PCI Configuration Access Data Register (Address: 0x03B)
4.3.1. Avalon® Streaming Interface
4.3.2. Precision Time Measurement (PTM) Interface (Endpoint Only)
4.3.3. Hot Plug Interface
4.3.4. Interrupt Interface
4.3.5. Hard IP Reconfiguration Interface
4.3.6. Error Interface
4.3.7. Completion Timeout Interface
4.3.8. Configuration Intercept Interface
4.3.9. Power Management Interface
4.3.10. Hard IP Status Interface
4.3.11. Page Request Services (PRS) Interface (Endpoint Only)
4.3.12. Function-Level Reset (FLR) Interface (Endpoint Only)
4.3.13. SR-IOV VF Error Flag Interface (Endpoint Only)
4.3.14. General Purpose VSEC Interface
5.2.3.1. Device Capabilities
5.2.3.2. VirtIO Parameters
5.2.3.3. Link Capabilities
5.2.3.4. Legacy Interrupt Pin Register
5.2.3.5. MSI Capabilities
5.2.3.6. MSI-X Capabilities
5.2.3.7. Slot Capabilities
5.2.3.8. Latency Tolerance Reporting (LTR)
5.2.3.9. Process Address Space ID (PASID)
5.2.3.10. Device Serial Number Capability
5.2.3.11. Page Request Service (PRS)
5.2.3.12. Access Control Service (ACS)
5.2.3.13. Power Management
5.2.3.14. Vendor Specific Extended Capability (VSEC) Registers
5.2.3.15. TLP Processing Hints (TPH)
5.2.3.16. Address Translation Services (ATS) Capabilities
5.2.3.17. Precision Time Measurement (PTM)
4.3.4.2. MSI
MSI interrupts are signaled on the PCI Express link using a single-dword Memory Write TLP. The user application issues an MSI request (MWr) through the Avalon® -ST interface and updates the configuration space register using the MSI interface.
Note: Only Ports 0 and 1 support MSI.
The suggested flow for sending an MSI is as follows:
- Form an MSI MemWr TLP with information (MSI addr/data) contained in the MSI Capability Structure (read from the HIP Reconfiguration Interface or Configuration Intercept Interface).
- Check the Mask bit of the interrupt vector of that function (Configuration intercept interface or HIP reconfiguration interface).
- Register: Mask Bits Register for MSI (MSI Capability Structure)
- If Mask is clear (bit = 1'b0):
- Send the MSI MemWr TLP (pending bit not required).
- If Mask is set (bit = 1'b1):
- Set the pending bit for the interrupt vector of the function (wait for pX_msi_pnd_ready_o=1'b1) via the MSI Interface (pX_msi_pnd_*) signals.
- If pX_msi_pnd_ready=0, wait until ready is high, and hold data for 1 cycle to set the pending bit.
- Wait for mask to be cleared (*).
- Monitor the mask register via CII.
- Once the Mask bit is clear, send the MSI MemWr TLP.
- Clear the pending bit for the interrupt vector.
Note: (*) Other vectors can set msi_pnd/send MSI in parallel while other vectors are waiting for masks to get cleared. - Set the pending bit for the interrupt vector of the function (wait for pX_msi_pnd_ready_o=1'b1) via the MSI Interface (pX_msi_pnd_*) signals.
Signal Name | Direction | Description | EP/RP/BP | Clock Domain |
---|---|---|---|---|
pX_msi_pnd_func_i[2:0] | Input | Function number select for the Pending Bits register in the MSI capability structure. | EP/BP | slow_clk |
pX_msi_pnd_addr_i[1:0] | Input | Byte select for the Pending Bits Register in the MSI Capability Structure. For example, if msi_pnd_addr_i[1:0] = 00, bits [7:0] of the Pending Bits register will be updated with msi_pnd_byte_i[7:0]. If msi_pnd_addr_i[1:0] = 01, bits [15:8] of the Pending Bits register will be updated with msi_pnd_byte_i[7:0]. | EP/BP | slow_clk |
pX_msi_pnd_byte_i[7:0] | Input | Indicate that function has a pending associated message. | EP | slow_clk |
pX_msi_pnd_ready_o | Output | A value of 0 indicates the endpoint may be servicing another message, and unable to service this master immediately. A new MSI pending bit event should be held until msi_pnd_ready_o = 1. |
EP/BP | slow_clk |