R-Tile Avalon® Streaming FPGA IP for PCI Express* User Guide

ID 683501
Date 8/11/2025
Public
Document Table of Contents

4.3.4.2. MSI

MSI interrupts are signaled on the PCI Express link using a single-dword Memory Write TLP. The user application issues an MSI request (MWr) through the Avalon® -ST interface and updates the configuration space register using the MSI interface.

Note: Only Ports 0 and 1 support MSI.
The suggested flow for sending an MSI is as follows:
  1. Form an MSI MemWr TLP with information (MSI addr/data) contained in the MSI Capability Structure (read from the HIP Reconfiguration Interface or Configuration Intercept Interface).
  2. Check the Mask bit of the interrupt vector of that function (Configuration intercept interface or HIP reconfiguration interface).
    • Register: Mask Bits Register for MSI (MSI Capability Structure)
  3. If Mask is clear (bit = 1'b0):
    • Send the MSI MemWr TLP (pending bit not required).
  4. If Mask is set (bit = 1'b1):
    • Set the pending bit for the interrupt vector of the function (wait for pX_msi_pnd_ready_o=1'b1) via the MSI Interface (pX_msi_pnd_*) signals.
      • If pX_msi_pnd_ready=0, wait until ready is high, and hold data for 1 cycle to set the pending bit.
    • Wait for mask to be cleared (*).
      1. Monitor the mask register via CII.
      2. Once the Mask bit is clear, send the MSI MemWr TLP.
    • Clear the pending bit for the interrupt vector.
    Note: (*) Other vectors can set msi_pnd/send MSI in parallel while other vectors are waiting for masks to get cleared.
Table 65.  MSI Interface Signals
Signal Name Direction Description EP/RP/BP Clock Domain
pX_msi_pnd_func_i[2:0] Input Function number select for the Pending Bits register in the MSI capability structure. EP/BP slow_clk
pX_msi_pnd_addr_i[1:0] Input Byte select for the Pending Bits Register in the MSI Capability Structure. For example, if msi_pnd_addr_i[1:0] = 00, bits [7:0] of the Pending Bits register will be updated with msi_pnd_byte_i[7:0]. If msi_pnd_addr_i[1:0] = 01, bits [15:8] of the Pending Bits register will be updated with msi_pnd_byte_i[7:0]. EP/BP slow_clk
pX_msi_pnd_byte_i[7:0] Input Indicate that function has a pending associated message. EP slow_clk
pX_msi_pnd_ready_o Output

A value of 0 indicates the endpoint may be servicing another message, and unable to service this master immediately.

A new MSI pending bit event should be held until msi_pnd_ready_o = 1.

EP/BP slow_clk