Answers to Top FAQs
1. Introduction to Quartus® Prime Pro Edition
2. Quick Start Steps
3. Planning FPGA Design for RTL Flow
4. Working With Altera IP Cores
5. Creating a New FPGA Design Project
6. Migrate Your FPGA Design Project
7. Managing Quartus® Prime Projects
8. Next Steps After Getting Started
A. Using the Design Space Explorer II
B. Document Revision History for Quartus® Prime Pro Edition User Guide Getting Started
4.1. Altera IP Catalog and Parameter Editor
4.2. Installing and Licensing Altera IP Cores
4.3. IP General Settings
4.4. Adding IP to IP Catalog
4.5. Best Practices for Altera IP
4.6. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition)
4.7. IP Core Generation Output ( Quartus® Prime Pro Edition)
4.8. Scripting IP Core Generation
4.9. Modifying an IP Variation
4.10. Upgrading IP Cores
4.11. Simulating Altera IP Cores
4.12. Generating Simulation Files for Platform Designer Systems and IP Variants
4.13. Synthesizing IP Cores in Other EDA Tools
4.14. Instantiating IP Cores in HDL
4.15. Support for the IEEE 1735 Encryption Standard
4.16. Related Trainings and Resources
6.1.2.1. Modifying Entity Name Assignments
6.1.2.2. Resolving Timing Constraint Entity Names
6.1.2.3. Verifying Generated Node Name Assignments
6.1.2.4. Replace Logic Lock (Standard) Regions
6.1.2.5. Modifying Signal Tap Logic Analyzer Files
6.1.2.6. Removing References to .qip Files
6.1.2.7. Removing Unsupported Feature Assignments
6.1.4.1. Verifying Verilog Compilation Unit
6.1.4.2. Updating Entity Auto-Discovery
6.1.4.3. Ensuring Distinct VHDL Namespace for Each Library
6.1.4.4. Removing Unsupported Parameter Passing
6.1.4.5. Removing Unsized Constant from WYSIWYG Instantiation
6.1.4.6. Removing Non-Standard Pragmas
6.1.4.7. Declaring Objects Before Initial Values
6.1.4.8. Confining SystemVerilog Features to SystemVerilog Files
6.1.4.9. Avoiding Assignment Mixing in Always Blocks
6.1.4.10. Avoiding Unconnected, Non-Existent Ports
6.1.4.11. Avoiding Invalid Parameter Ranges
6.1.4.12. Updating Verilog HDL and VHDL Type Mapping
6.1.4.13. Converting Symbolic BDF Files to Acceptable File Formats
7.1. Viewing Basic Project Information
7.2. Managing Project Settings
7.3. Viewing Parameter Settings From the Project Navigator
7.4. Managing Logic Design Files
7.5. Managing Timing Constraints
7.6. Integrating Other EDA Tools
7.7. Exporting Compilation Results
7.8. Archiving Projects
7.9. Command-Line Interface
7.10. Related Trainings
7.7.1. Exporting a Version-Compatible Compilation Database
7.7.2. Importing a Version-Compatible Compilation Database
7.7.3. Creating a Design Partition
7.7.4. Exporting a Design Partition
Manual Design Partition Export
Automated Design Partition Export
7.7.5. Reusing a Design Partition
7.7.6. Viewing Quartus Database File Information
7.7.7. Clearing Compilation Results
7.7.4. Exporting a Design Partition
The following steps describe export of design partitions that you create in your project.
Note: Design partitions exported from the Quartus® Prime Pro Edition software versions 23.2 or earlier cannot be imported into version 23.3 or later due to the new DNI database.
When you compile a design containing design partitions, the Compiler can preserve a synthesis or final snapshot of results for each partition. You can export the synthesized or final compilation results for individual design partitions with the Export Design Partition dialog box.
If the partition includes any entity-bound .sdc files, you can include those constraints in the .qdb. In addition, you can automate export of one or more partitions in the Design Partitions Window.
Manual Design Partition Export
Follow these steps to manually export a design partition with the Export Design Partition dialog box:
- Open a project and create one or more design partitions. Creating a Design Partition describes this process.
- Run synthesis (Processing > Start > Start Analysis & Synthesis) or full compilation (Processing > Start Compilation), depending on which compilation results that you want to export.
- Click Project > Export Design Partition, and specify one or more options in the Export Design Partition dialog box:
Figure 59. Export Design Partition Dialog Box
- Select the Partition name and the compilation Snapshot for export.
- To include any entity-bound .sdc files in the exported .qdb, turn on Include entity-bound SDC files for the selected partition.
- Click OK. The compilation results for the design partition exports to the file that you specify.
Automated Design Partition Export
Follow these steps to automatically export one or more design partitions following each compilation:
- Open a project containing one or more design partitions. Creating a Design Partition describes this process.
- To open the Design Partitions Window, click Assignments > Design Partitions Window.
- To automatically export a partition with synthesis results after each time you run synthesis, specify the a .qdb export path and file name for the Post Synthesis Export File option for that partition. If you specify only a file name without a path, the file exports to the output_files directory after compilation.
- To automatically export a partition with final snapshot results each time you run the Fitter, specify a .qdb file name for the Post Final Export File option for that partition. If you specify only a file name without a path, the file exports to the output_files directory after compilation.
Figure 60. Specifying Export File in Design Partitions Window
.qsf Equivalent Assignment:
set_instance_assignment -name EXPORT_PARTITION_SNAPSHOT_<FINAL|SYNTHESIZED> \ <file_name>.qdb -to <hpath>