Hyperflex® Architecture High-Performance Design Handbook
ID
683353
Date
7/07/2025
Public
Answers to Top FAQs
1. Hyperflex® FPGA Architecture Introduction
2. Hyperflex® Architecture RTL Design Guidelines
3. Compiling Hyperflex® Architecture Designs
4. Design Example Walk-Through
5. Retiming Restrictions and Workarounds
6. Optimization Example
7. Hyperflex® Architecture Porting Guidelines
8. Appendices
9. Hyperflex® Architecture High-Performance Design Handbook Archive
10. Hyperflex® Architecture High-Performance Design Handbook Revision History
2.4.2.1. High-Speed Clock Domains
2.4.2.2. Restructuring Loops
2.4.2.3. Control Signal Backpressure
2.4.2.4. Flow Control with FIFO Status Signals
2.4.2.5. Flow Control with Skid Buffers
2.4.2.6. Read-Modify-Write Memory
2.4.2.7. Counters and Accumulators
2.4.2.8. State Machines
2.4.2.9. Memory
2.4.2.10. DSP Blocks
2.4.2.11. General Logic
2.4.2.12. Modulus and Division
2.4.2.13. Resets
2.4.2.14. Hardware Re-use
2.4.2.15. Algorithmic Requirements
2.4.2.16. FIFOs
2.4.2.17. Ternary Adders
Ternary Adder RTL Code
5.2.1. Insufficient Registers
5.2.2. Short Path/Long Path
5.2.3. Fast Forward Limit
5.2.4. Loops
5.2.5. One Critical Chain per Clock Domain
5.2.6. Critical Chains in Related Clock Groups
5.2.7. Complex Critical Chains
5.2.8. Extend to locatable node
5.2.9. Domain Boundary Entry and Domain Boundary Exit
5.2.10. Critical Chains with Dual Clock Memories
5.2.11. Critical Chain Bits and Buses
5.2.12. Delay Lines
2.4.2.17. Ternary Adders
Implementing ternary adders can increase resource usage in Hyperflex® architecture FPGAs. However, unless your design heavily relies on ternary adder structure, additional resource usage may not be noticeable at the top design level. However, a review of the design level at which you add a ternary adder structure can show an increase in LUT count. In addition, the amount of resource increase directly correlates to the size of the adder. Small width adders (size < 16 bits) do not cause much resource difference. However, increasing the size of the adder increases the resource count differential, in comparison with older FPGA technology.
Ternary Adder RTL Code
module ternary_adder (CLK, A, B, C, OUT); parameter WIDTH = 16; input [WIDTH-1:0] A, B, C; input CLK; output [WIDTH-1:0] OUT; wire [WIDTH-1:0] sum1; reg [WIDTH-1:0] sumreg1; // 3-bit additions assign sum1 = A + B + C; assign OUT = sumreg1; // Registers always @ (posedge CLK) begin sumreg1 <= sum1; end endmodule
This increase in device resource use occurs because the Hyperflex® architecture ALM does not have a shared arithmetic mode that previous FPGA technologies have. The ALM in shared arithmetic mode can implement a three-input add in the ALM. By contrast, the Hyperflex® architecture ALM can implement only a two-input add in the ALM.
Figure 82. RTL View of Arria® 10 versus Hyperflex® Architecture FPGAs to add 2 LSBs from a three 8-bit input adder
In shared arithmetic mode, the Arria® 10 ALM allows a three-input adder to use three adaptive LUT (ALUT) inputs: CIN, SHAREIN, COUT, SUMOUT, and SHAREOUT. The absence of the shared arithmetic mode restricts ALM use with only two ALUT inputs: CIN, COUT and SUMOUT. The figure below shows the resulting implementation of a ternary adder on both Arria® 10 and Hyperflex® architecture FPGAs.
Figure 83. Arria® 10: ALMs used to add 2 LSBs from a three 8-bit input adder
Figure 84. Hyperflex® Architecture FPGAs: ALMs used to add 2 LSBs from a three 8-bit input adder