Intel® Hyperflex™ Architecture High-Performance Design Handbook

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Date 12/08/2023
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Intel® Hyperflex™ FPGA Architecture Introduction 2. Intel® Hyperflex™ Architecture RTL Design Guidelines 3. Compiling Intel® Hyperflex™ Architecture Designs 4. Design Example Walk-Through 5. Retiming Restrictions and Workarounds 6. Optimization Example 7. Intel® Hyperflex™ Architecture Porting Guidelines 8. Appendices 9. Intel® Hyperflex™ Architecture High-Performance Design Handbook Archive 10. Intel® Hyperflex™ Architecture High-Performance Design Handbook Revision History
1. Intel® Hyperflex™ FPGA Architecture Introduction x
1.1. Intel® Hyperflex™ Architecture Design Concepts
2. Intel® Hyperflex™ Architecture RTL Design Guidelines x
2.1. High-Speed Design Methodology 2.2. Hyper-Retiming (Facilitate Register Movement) 2.3. Hyper-Pipelining (Add Pipeline Registers) 2.4. Hyper-Optimization (Optimize RTL)
2.1. High-Speed Design Methodology x
2.1.1. Set a High-Speed Target 2.1.2. Experiment and Iterate 2.1.3. Compile Components Independently 2.1.4. Optimize Sub-Modules 2.1.5. Avoid Broadcast Signals
2.1.1. Set a High-Speed Target x
2.1.1.1. Speed and Timing Closure 2.1.1.2. Speed and Latency
2.2. Hyper-Retiming (Facilitate Register Movement) x
2.2.1. Reset Strategies 2.2.2. Clock Enable Strategies 2.2.3. Preserving Registers During Synthesis 2.2.4. Timing Constraint Considerations 2.2.5. Clock Synchronization Strategies 2.2.6. Metastability Synchronizers 2.2.7. Initial Power-Up Conditions 2.2.8. Retiming through RAMs and DSPs
2.2.1. Reset Strategies x
2.2.1.1. Removing Asynchronous Resets 2.2.1.2. Synchronous Resets on Global Clock Trees 2.2.1.3. Synchronous Resets on I/O Ports 2.2.1.4. Duplicate and Pipeline Synchronous Resets
2.2.2. Clock Enable Strategies x
2.2.2.1. Localized Clock Enable 2.2.2.2. High Fan-Out Clock Enable 2.2.2.3. Clock Enable with Timing Exceptions
2.2.4. Timing Constraint Considerations x
2.2.4.1. Optimize Multicycle Paths 2.2.4.2. Overconstraints
2.2.5. Clock Synchronization Strategies x
2.2.5.1. Clock Domain Crossing Constraint Guidelines
2.2.7. Initial Power-Up Conditions x
2.2.7.1. Specifying Initial Memory Conditions 2.2.7.2. Initial Conditions and Retiming 2.2.7.3. Initial Conditions and Hyper-Registers 2.2.7.4. Retiming Reset Sequences
2.2.7.3. Initial Conditions and Hyper-Registers x
2.2.7.3.1. Implementing Clock Gating 2.2.7.3.2. Intel® Quartus® Prime Settings for Initial Conditions
2.3. Hyper-Pipelining (Add Pipeline Registers) x
2.3.1. Conventional Versus Hyper-Pipelining 2.3.2. Pipelining and Latency 2.3.3. Use Registers Instead of Multicycle Exceptions
2.3.2. Pipelining and Latency x
2.3.2.1. Pipelining at Variable Latency Locations 2.3.2.2. Automatic Pipeline Insertion
2.3.2.1. Pipelining at Variable Latency Locations x
2.3.2.1.1. Specifying a Latency-Insensitive False Path
2.3.2.2. Automatic Pipeline Insertion x
2.3.2.2.1. Step 1: Create the Variable Latency Module 2.3.2.2.2. Step 2: Instantiate the Variable Latency Module 2.3.2.2.3. Step 3: Verify Automatic Pipeline Insertion Option 2.3.2.2.4. (Optional) Auto-Pipeline Insertion without a Variable Latency Module
2.4. Hyper-Optimization (Optimize RTL) x
2.4.1. General Optimization Techniques 2.4.2. Optimizing Specific Design Structures
2.4.1. General Optimization Techniques x
2.4.1.1. Shannon’s Decomposition 2.4.1.2. Time Domain Multiplexing 2.4.1.3. Loop Unrolling 2.4.1.4. Loop Pipelining 2.4.1.5. Precomputation
2.4.1.1. Shannon’s Decomposition x
2.4.1.1.1. Shannon’s Decomposition Example 2.4.1.1.2. Identifying Circuits for Shannon’s Decomposition
2.4.1.4. Loop Pipelining x
2.4.1.4.1. Loop Pipelining Theory 2.4.1.4.2. Loop Pipelining Demonstration 2.4.1.4.3. Loop Pipelining and Synthesis Optimization
2.4.2. Optimizing Specific Design Structures x
2.4.2.1. High-Speed Clock Domains 2.4.2.2. Restructuring Loops 2.4.2.3. Control Signal Backpressure 2.4.2.4. Flow Control with FIFO Status Signals 2.4.2.5. Flow Control with Skid Buffers 2.4.2.6. Read-Modify-Write Memory 2.4.2.7. Counters and Accumulators 2.4.2.8. State Machines 2.4.2.9. Memory 2.4.2.10. DSP Blocks 2.4.2.11. General Logic 2.4.2.12. Modulus and Division 2.4.2.13. Resets 2.4.2.14. Hardware Re-use 2.4.2.15. Algorithmic Requirements 2.4.2.16. FIFOs 2.4.2.17. Ternary Adders
2.4.2.1. High-Speed Clock Domains x
2.4.2.1.1. Visualizing Clock Networks 2.4.2.1.2. Viewing Clock Networks in the Fitter Report 2.4.2.1.3. Viewing Clocks in the Timing Analyzer
2.4.2.9. Memory x
2.4.2.9.1. Intel® Hyperflex™ Architecture True Dual-Port Memory 2.4.2.9.2. Use Simple Dual-Port Memories 2.4.2.9.3. Intel® Hyperflex™ Architecture Simple Dual-Port Memory Example 2.4.2.9.4. Memory Mixed Port Width Ratio Limits 2.4.2.9.5. Unregistered RAM Outputs
3. Compiling Intel® Hyperflex™ Architecture Designs x
3.1. Compiling Submodules Independently 3.2. Design Assistant Design Rule Checking
3.2. Design Assistant Design Rule Checking x
3.2.1. Running Design Assistant During Compilation 3.2.2. Running Design Assistant in Analysis Mode
3.2.2. Running Design Assistant in Analysis Mode x
3.2.2.1. Cross-Probing from Design Assistant to Visualization Tools 3.2.2.2. Launching Design Assistant from Chip Planner 3.2.2.3. Launching Design Assistant from Timing Analyzer
4. Design Example Walk-Through x
4.1. Median Filter Design Example
4.1. Median Filter Design Example x
4.1.1. Step 1: Compile the Base Design 4.1.2. Step 2: Add Pipeline Stages and Remove Asynchronous Resets 4.1.3. Step 3: Add More Pipeline Stages and Remove All Asynchronous Resets 4.1.4. Step 4: Optimize Short Path and Long Path Conditions
5. Retiming Restrictions and Workarounds x
5.1. Setting the dont_merge Synthesis Attribute 5.2. Interpreting Critical Chain Reports
5.2. Interpreting Critical Chain Reports x
5.2.1. Insufficient Registers 5.2.2. Short Path/Long Path 5.2.3. Fast Forward Limit 5.2.4. Loops 5.2.5. One Critical Chain per Clock Domain 5.2.6. Critical Chains in Related Clock Groups 5.2.7. Complex Critical Chains 5.2.8. Extend to locatable node 5.2.9. Domain Boundary Entry and Domain Boundary Exit 5.2.10. Critical Chains with Dual Clock Memories 5.2.11. Critical Chain Bits and Buses 5.2.12. Delay Lines
5.2.1. Insufficient Registers x
5.2.1.1. Insufficient Registers Example 5.2.1.2. Optimizing Insufficient Registers 5.2.1.3. Critical Chains with Dual Clock Memories
5.2.2. Short Path/Long Path x
5.2.2.1. Hyper-Register Locations Not Available 5.2.2.2. Example for Hold Optimization 5.2.2.3. Optimizing Short Path/Long Path 5.2.2.4. Add Registers 5.2.2.5. Duplicate Common Nodes 5.2.2.6. Data and Control Plane
5.2.3. Fast Forward Limit x
5.2.3.1. Optimizing Path Limit
5.2.4. Loops x
5.2.4.1. Example of Loops Limiting the Critical Chain
6. Optimization Example x
6.1. Round Robin Scheduler
7. Intel® Hyperflex™ Architecture Porting Guidelines x
7.1. Design Migration and Performance Exploration 7.2. Top-Level Design Considerations
7.1. Design Migration and Performance Exploration x
7.1.1. Black-boxing Verilog HDL Modules 7.1.2. Black-boxing VHDL Modules 7.1.3. Clock Management 7.1.4. Pin Assignments 7.1.5. Transceiver Control Logic 7.1.6. Upgrade Outdated IP Cores
8. Appendices x
8.1. Appendix A: Parameterizable Pipeline Modules 8.2. Appendix B: Clock Enables and Resets
8.2. Appendix B: Clock Enables and Resets x
8.2.1. Synchronous Resets and Limitations 8.2.2. Retiming with Clock Enables 8.2.3. Resolving Short Paths
8.2.1. Synchronous Resets and Limitations x
8.2.1.1. Synchronous Resets Summary
8.2.2. Retiming with Clock Enables x
8.2.2.1. Example for Broadcast Control Signals
Answers to Top FAQs
1. Intel® Hyperflex™ FPGA Architecture Introduction
2. Intel® Hyperflex™ Architecture RTL Design Guidelines
3. Compiling Intel® Hyperflex™ Architecture Designs
4. Design Example Walk-Through
5. Retiming Restrictions and Workarounds
6. Optimization Example
7. Intel® Hyperflex™ Architecture Porting Guidelines
8. Appendices
9. Intel® Hyperflex™ Architecture High-Performance Design Handbook Archive
10. Intel® Hyperflex™ Architecture High-Performance Design Handbook Revision History

6.1. Round Robin Scheduler

The round robin scheduler is a basic functional block. The following example uses a modulus operator to determine the next client for service. The modulus operator is relatively slow and area inefficient because the modulus operator performs division.

Source Code for Round Robin Scheduler

module round_robin_modulo (last, requests, next);

parameter CLIENTS       = 7;
parameter LOG2_CLIENTS  = 3;

// previous client to be serviced
input wire [LOG2_CLIENTS -1:0]  last;
// Client requests:- 
input wire [CLIENTS -1:0] requests;
// Next client to be serviced: -
output reg [LOG2_CLIENTS -1:0] next;


//Schedule the next client in a round robin fashion, based on the previous
always @*
begin
   integer J, K;

   begin : find_next
   next = last; // Default to staying with the previous
   for (J = 1; J < CLIENTS; J=J+1)
      begin
      K = (last + J) % CLIENTS;
      if (requests[K] == 1'b1)
         begin
         	 next = K[0 +: LOG2_CLIENTS];
         	 disable find_next;
       	 end
		end // of the for-loop
    end   // of 'find_next'
end 

 endmodule
Figure 125. Fast Forward Compile Report for Round Robin Scheduler

The Retiming Summary report identifies insufficient registers limiting Hyper-Retiming on the critical chain. The chain starts from the register that connects to the last input, through the modulus operator implemented using a divider, and continuing to the register that connects to the next output.

Figure 126. Critical Chain for Base Performance for Round Robin Scheduler

The 44 elements in the critical chain above correspond to the circuit diagram below that has 10 levels of logic. The modulus operator contributes significantly to the low performance. Seven of the 10 levels of logic are part of the implementation for the modulus operator.

Figure 127. Schematic for Critical Chain

As Figure 125 shows, Fast Forward compilation estimates a 140% performance improvement from adding two pipeline stages at the module inputs, for retiming through the logic cloud. At this point, the critical chain is a short path/long path and the chain involves the modulus operator.

Figure 128. Critical Chain Fast Forward Compile for Round Robin Scheduler

The divider in the modulus operation is the bottleneck that requires RTL modification. Paths through the divider exist in the critical chain for all steps in the Fast Forward compile. Consider alternate implementations to calculate the next client to service, and avoid the modulus operator. If you switch to an implementation that specifies the number of clients as a power of two, determining the next client to service does not require a modulus operator. When you instantiate the module with fewer than 2n clients, tie the unused request inputs to logic 0.

Source Code for Round Robin Scheduler with Performance Improvement with 2n Client Inputs 

module round_robin_modulo (last, requests, next);

parameter LOG2_CLIENTS  = 3;
parameter CLIENTS       = 2**LOG2_CLIENTS;

// previous client to be serviced
input wire [LOG2_CLIENTS -1:0]  last;
// Client requests:- 
input wire [CLIENTS -1:0] requests;
// Next client to be serviced: -
output reg [LOG2_CLIENTS -1:0] next;


//Schedule the next client in a round robin fashion, based on the previous
always @(next or last or requests)
begin
   integer J, K;

   begin : find_next
   next = last; // Default to staying with the previous
   for (J = 1; J < CLIENTS; J=J+1)
      begin
      K = last + J;
      if (requests[K[0 +: LOG2_CLIENTS]] == 1'b1)
         begin
         	 next = K[0 +: LOG2_CLIENTS];
         	 disable find_next;
       	 end
	end // of the for-loop
  end   // of 'find_next'
end

 endmodule
Figure 129. Fast Forward Summary Report for Round Robin Scheduler with Performance Improvement with 2n Client Inputs

Even without any Fast Forward optimizations (the Base Performance step), this round robin implementation runs at double the frequency compared with the version without the performance improvement in Source Code for Round Robin Scheduler. Although critical chains in both versions contain only two registers, the critical chain for the 2n version contains only 26 elements, compared to 44 elements in the modulus version.

Figure 130. Critical Chain for Round Robin Scheduler with Performance Improvement

The 26 elements in the critical chain correspond to the following circuit diagram with only four levels of logic.

Figure 131. Schematic for Critical Chain with Performance Improvement

By adding three register stages at the input, for retiming through the logic cloud, Fast Forward Compile takes the circuit performance to 1 GHz. Similar to the modulus version, the final critical chain after Fast Forward optimization has a limiting reason of short path/long path, as Figure 132 shows, but the performance is 1.6 times the performance of the modulus version

Figure 132. Critical Chain for Round Robin Scheduler with Best Performance

Removing the modulus operator, and switching to a power-of-two implementation, are small design changes that provide a dramatic performance increase.

  • Use natural powers of two for math operations whenever possible
  • Explore alternative implementations for seemingly basic functions.

In this example, changing the implementation of the round robin logic provides more performance increase than adding pipeline stages.

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