SDI Audio IP User Guide

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ID 683333
Date 6/15/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the SDI Audio IP 2. SDI Audio IP Getting Started 3. SDI Audio Altera FPGA IP Functional Description 4. SDI Audio Altera FPGA IP Parameters 5. SDI Audio Altera FPGA IP Interface Signals 6. SDI Audio Altera FPGA IP Registers 7. SDI Audio IP User Guide Archives 8. Document Revision History for the SDI Audio IP User Guide
1. About the SDI Audio IP x
1.1. SDI Audio IP Device Support 1.2. SDI Audio IP Release Information 1.3. SDI Audio IP Performance and Resources
2. SDI Audio IP Getting Started x
2.1. Instantiating the SDI Audio Altera FPGA IP Simulating the Testbench
3. SDI Audio Altera FPGA IP Functional Description x
3.1. SDI Audio Embed IP 3.2. SDI Audio Extract IP 3.3. SDI Clocked Audio Input IP 3.4. SDI Clocked Audio Output IP 3.5. AES Format 3.6. Avalon Streaming Interface Audio Interface
4. SDI Audio Altera FPGA IP Parameters x
4.1. SDI Audio Embed IP Parameters 4.2. SDI Audio Extract IP Parameters 4.3. SDI Clocked Audio Input IP Parameters 4.4. SDI Clocked Audio Output IP Parameters
5. SDI Audio Altera FPGA IP Interface Signals x
5.1. SDI Audio Embed IP Signals 5.2. SDI Audio Extract IP Signals 5.3. SDI Audio Clocked Input Signals 5.4. SDI Audio Clocked Output Signals 5.5. SDI Audio IP Register Interface Signals
6. SDI Audio Altera FPGA IP Registers x
6.1. SDI Audio Embed Registers 6.2. SDI Audio Extract Registers 6.3. SDI Clocked Audio Input Registers 6.4. SDI Clocked Audio Output Registers
1. About the SDI Audio IP
2. SDI Audio IP Getting Started
3. SDI Audio Altera FPGA IP Functional Description
4. SDI Audio Altera FPGA IP Parameters
5. SDI Audio Altera FPGA IP Interface Signals
6. SDI Audio Altera FPGA IP Registers
7. SDI Audio IP User Guide Archives
8. Document Revision History for the SDI Audio IP User Guide

3.2. SDI Audio Extract IP

The SDI Audio Extract IP accepts the SD-, HD-, and 3G-SDI from the SDI IPs and extracts one channel pair of embedded audio.

The format of the embedded audio is in accordance with the following standards:

  • SMPTE272M-ABCD standard for SD-SDI
  • SMPTE299M standard for HD-SDI
  • SMPTE299M standard for 3G-SDI (provisional)

If you are extracting more than one channel pair, you must use multiple instances of the component. This IP supports AES audio format for a 48 kHz sampling rate.

Figure 2. SDI Audio Extract IP Block Diagram

The SDI Audio Extract IP consists of the following components:

  • An audio extraction IP
  • A register interface block that provides support for an Avalon® memory-mapped interface control bus

The clock recovery block recreates a 64 × sample rate clock, which you can use to clock the audio output logic. As the component recreates this clock from a 200 MHz reference clock, the created clock may have a higher jitter than is desirable.

A digital PLL synchronizes this created clock to a 24 kHz reference source.

For the HD-SDI embedded audio, the 24 kHz reference source is the embedded clock phase information.

For the SD-SDI embedded audio, where the embedded clock phase data is not present, you can create the 24 kHz reference signal directly from the video clock.

Figure 3. IP Recovery Block Diagram
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