SDI Audio IP User Guide

Download PDF
ID 683333
Date 6/15/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the SDI Audio IP 2. SDI Audio IP Getting Started 3. SDI Audio Altera FPGA IP Functional Description 4. SDI Audio Altera FPGA IP Parameters 5. SDI Audio Altera FPGA IP Interface Signals 6. SDI Audio Altera FPGA IP Registers 7. SDI Audio IP User Guide Archives 8. Document Revision History for the SDI Audio IP User Guide
1. About the SDI Audio IP x
1.1. SDI Audio IP Device Support 1.2. SDI Audio IP Release Information 1.3. SDI Audio IP Performance and Resources
2. SDI Audio IP Getting Started x
2.1. Instantiating the SDI Audio Altera FPGA IP Simulating the Testbench
3. SDI Audio Altera FPGA IP Functional Description x
3.1. SDI Audio Embed IP 3.2. SDI Audio Extract IP 3.3. SDI Clocked Audio Input IP 3.4. SDI Clocked Audio Output IP 3.5. AES Format 3.6. Avalon Streaming Interface Audio Interface
4. SDI Audio Altera FPGA IP Parameters x
4.1. SDI Audio Embed IP Parameters 4.2. SDI Audio Extract IP Parameters 4.3. SDI Clocked Audio Input IP Parameters 4.4. SDI Clocked Audio Output IP Parameters
5. SDI Audio Altera FPGA IP Interface Signals x
5.1. SDI Audio Embed IP Signals 5.2. SDI Audio Extract IP Signals 5.3. SDI Audio Clocked Input Signals 5.4. SDI Audio Clocked Output Signals 5.5. SDI Audio IP Register Interface Signals
6. SDI Audio Altera FPGA IP Registers x
6.1. SDI Audio Embed Registers 6.2. SDI Audio Extract Registers 6.3. SDI Clocked Audio Input Registers 6.4. SDI Clocked Audio Output Registers
1. About the SDI Audio IP
2. SDI Audio IP Getting Started
3. SDI Audio Altera FPGA IP Functional Description
4. SDI Audio Altera FPGA IP Parameters
5. SDI Audio Altera FPGA IP Interface Signals
6. SDI Audio Altera FPGA IP Registers
7. SDI Audio IP User Guide Archives
8. Document Revision History for the SDI Audio IP User Guide

5.4. SDI Audio Clocked Output Signals

Table 23.  SDI Audio Clocked Output Input and Output Signals
Signal Width Direction Description
aes_clk [0:0] Input Audio input clock.
aes_de [0:0] Output Audio data enable.
aes_ws [0:0] Output Audio word select.
aes_data [0:0] Output Audio data input in internal AES format.
Table 24.  SDI Audio Clocked Output Avalon-ST Audio SignalsThis table lists the Avalon streaming interface audio signals when you instantiate the SDI Audio Clocked Output IP core in Platform Designer (Standard).
Signal Width Direction Description
aud_clk [0:0] Input Clocked audio clock. All the audio input signals are synchronous to this clock.
aud_ready [0:0] Output Avalon streaming interface ready signal. Assert this signal when the device is able to receive data.
aud_valid [0:0] Input Avalon streaming interface valid signal. The core asserts this signal when it receives data.
aud_sop [0:0] Input Avalon streaming interface start of packet signal. The core asserts this signal when it is starting a new frame.
aud_eop [0:0] Input Avalon streaming interface end of packet signal. The core asserts this signal when it is ending a frame.
aud_data [23:0] Input Avalon streaming interface data bus. This bus transfers data.
Related Information
Level Two Title