Mailbox Client IPs User Guide

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ID 683290
Date 4/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client IPs User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client IPs User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Parameters 1.4. Mailbox Client IP Core Interface Signals 1.5. Mailbox Client IP Avalon® Memory-Mapped Interface 1.6. Commands and Responses 1.7. Specifying the Command and Response FIFO Depths 1.8. Enabling Cryptographic Services 1.9. Using the Mailbox Client IP 1.10. Accessing Quad SPI Flash Mailbox Client IP Core Use Case Examples 1.11. Nios® II and Nios® V Processors HAL Driver 1.12. Mailbox Client IP User Guide Archives 1.13. Document Revision History for the Mailbox Client IP User Guide
1.4. Mailbox Client IP Core Interface Signals x
1.4.1. Clock and Reset Interfaces 1.4.2. Avalon® Memory-Mapped Interface 1.4.3. AXI Manager Interface
1.5. Mailbox Client IP Avalon® Memory-Mapped Interface x
1.5.1. Interrupt Enable Register 1.5.2. Interrupt Status Register 1.5.3. Timer Registers
1.6. Commands and Responses x
1.6.1. Operation Commands 1.6.2. Error Code Responses 1.6.3. Error Code Recovery
1.11. Nios® II and Nios® V Processors HAL Driver x
1.11.1. Mailbox Client HAL API 1.11.2. LibRSU HAL API
1.11.1. Mailbox Client HAL API x
1.11.1.1. Mailbox Client Driver API
1.11.2. LibRSU HAL API x
1.11.2.1. Configuration Parameter 1.11.2.2. Error Codes 1.11.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.11.2.4. Data Type 1.11.2.5. Functions 1.11.2.6. RSU Client API
1. Mailbox Client IPs User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.5. Mailbox Client IP Avalon® Memory-Mapped Interface

Table 7.   Avalon® Memory-Mapped Interface
Offset (word) R/W 31 30:2 1 0
Base address + 0 W Command
Base address + 1 W Command last word (eop)
Base address + 2 R Command FIFO empty space
Base address + 3 N/A Reserved
Base address + 4 N/A Reserved
Base address + 5 R Response data
Base address + 6 R Response FIFO fill level EOP SOP
Base address + 7 R/W Interrupt enable register (IER)
Base address + 8 R Interrupt status register (ISR)
Base address + 9 R/W Timer 1 enable Timer 1 period
Base address + 10 R/W Timer 2 enable Timer 2 period

Section Content
Interrupt Enable Register
Interrupt Status Register
Timer Registers

Level Two Title