1.1.1. Timing Path and Clock Analysis
1.1.2. Clock Setup Analysis
1.1.3. Clock Hold Analysis
1.1.4. Recovery and Removal Analysis
1.1.5. Multicycle Path Analysis
1.1.6. Metastability Analysis
1.1.7. Timing Pessimism
1.1.8. Clock-As-Data Analysis
1.1.9. Multicorner Timing Analysis
1.1.10. Time Borrowing
2.1. Using Timing Constraints throughout the Design Flow
2.2. Timing Analysis Flow
2.3. Applying Timing Constraints
2.4. Timing Constraint Descriptions
2.5. Timing Report Descriptions
2.6. Scripting Timing Analysis
2.7. Using the Quartus® Prime Timing Analyzer Document Revision History
2.8. Quartus® Prime Pro Edition User Guide: Timing Analyzer Archive
2.4.4.5.1. Default Multicycle Analysis
2.4.4.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0
2.4.4.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1
2.4.4.5.4. Same Frequency Clocks with Destination Clock Offset
2.4.4.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency
2.4.4.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
2.4.4.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency
2.4.4.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
2.5.1. Report Fmax Summary
2.5.2. Report Timing
2.5.3. Report Timing By Source Files
2.5.4. Report Data Delay
2.5.5. Report Net Delay
2.5.6. Report Clocks and Clock Network
2.5.7. Report Clock Transfers
2.5.8. Report Metastability
2.5.9. Report CDC Viewer
2.5.10. Report Asynchronous CDC
2.5.11. Report Logic Depth
2.5.12. Report Neighbor Paths
2.5.13. Report Register Spread
2.5.14. Report Route Net of Interest
2.5.15. Report Retiming Restrictions
2.5.16. Report Register Statistics
2.5.17. Report Pipelining Information
2.5.18. Report Time Borrowing Data
2.5.19. Report Exceptions and Exceptions Reachability
2.5.20. Report Bottlenecks
2.5.21. Check Timing
2.5.22. Report SDC
2.5.23. Design Closure Summary
3.1.1. CDC Timing Overview
3.1.2. Identifying CDC Timing Issues Using Design Assistant
3.1.3. Identifying CDC Timing Issues Using Timing Reports
3.1.4. Debug CDC Example 1—Incorrect SDC Definition
3.1.5. Debug CDC Example 2—Additional Logic in the Crossing
3.1.6. Debug CDC Example 3—CDC Depending on Two Simultaneous Clock Domains
2.5.7. Report Clock Transfers
The Timing Analyzer's Reports > Clock Domain Crossings > Report Clock Transfers command reports all clock-to-clock transfers in the design. The equivalent scripting command is report_clock_transfers.
Report Clock Transfers generates the Setup Transfers report and the Hold Transfers report that display data about the clock-to-clock transfers.
Figure 159. Setup Transfers Report Shows Clock-to-Clock Transfers
The Setup Transfers report and Hold Transfers report display all possible transfers, including rising clock edge to rising clock edge (RR), falling clock edge to rising clock edge (FR), rising clock edge to falling clock edge (RF), and falling clock edge to falling clock edge (FF) paths.
- If a path exists in the design, the report column cell is white and lists the number of paths.
- If a path is a false path, the report column cell is light gray and contains the text "false path."
- If a path does not exist in the design, then the report column cell is dark gray.
The Setup Transfers report and Hold Transfers report also lists the Worst-Case Slack for setup, the Worst-Case Operating Conditions, and the Clock Pair Classification for each clock path. The Clock Pair Classification includes the following:
Clock Pair Classification | Definition |
---|---|
Intra-Clock (Timed Safe) |
|
Inter-Clock Synchronous (Timed Safe) |
|
Asynchronous (Timed Unsafe) |
|
Ignored (Not Timed) |
|