1.1.1. Timing Path and Clock Analysis
1.1.2. Clock Setup Analysis
1.1.3. Clock Hold Analysis
1.1.4. Recovery and Removal Analysis
1.1.5. Multicycle Path Analysis
1.1.6. Metastability Analysis
1.1.7. Timing Pessimism
1.1.8. Clock-As-Data Analysis
1.1.9. Multicorner Timing Analysis
1.1.10. Time Borrowing
2.1. Using Timing Constraints throughout the Design Flow
2.2. Timing Analysis Flow
2.3. Applying Timing Constraints
2.4. Timing Constraint Descriptions
2.5. Timing Report Descriptions
2.6. Scripting Timing Analysis
2.7. Using the Quartus® Prime Timing Analyzer Document Revision History
2.8. Quartus® Prime Pro Edition User Guide: Timing Analyzer Archive
2.4.4.5.1. Default Multicycle Analysis
2.4.4.5.2. End Multicycle Setup = 2 and End Multicycle Hold = 0
2.4.4.5.3. End Multicycle Setup = 2 and End Multicycle Hold = 1
2.4.4.5.4. Same Frequency Clocks with Destination Clock Offset
2.4.4.5.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency
2.4.4.5.6. Destination Clock Frequency is a Multiple of the Source Clock Frequency with an Offset
2.4.4.5.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency
2.4.4.5.8. Source Clock Frequency is a Multiple of the Destination Clock Frequency with an Offset
2.5.1. Report Fmax Summary
2.5.2. Report Timing
2.5.3. Report Timing By Source Files
2.5.4. Report Data Delay
2.5.5. Report Net Delay
2.5.6. Report Clocks and Clock Network
2.5.7. Report Clock Transfers
2.5.8. Report Metastability
2.5.9. Report CDC Viewer
2.5.10. Report Asynchronous CDC
2.5.11. Report Logic Depth
2.5.12. Report Neighbor Paths
2.5.13. Report Register Spread
2.5.14. Report Route Net of Interest
2.5.15. Report Retiming Restrictions
2.5.16. Report Register Statistics
2.5.17. Report Pipelining Information
2.5.18. Report Time Borrowing Data
2.5.19. Report Exceptions and Exceptions Reachability
2.5.20. Report Bottlenecks
2.5.21. Check Timing
2.5.22. Report SDC
2.5.23. Design Closure Summary
3.1.1. CDC Timing Overview
3.1.2. Identifying CDC Timing Issues Using Design Assistant
3.1.3. Identifying CDC Timing Issues Using Timing Reports
3.1.4. Debug CDC Example 1—Incorrect SDC Definition
3.1.5. Debug CDC Example 2—Additional Logic in the Crossing
3.1.6. Debug CDC Example 3—CDC Depending on Two Simultaneous Clock Domains
2.4.1.5.1. Exclusive Clock Groups (-logically_exclusive or -physically_exclusive)
You can use the logically_exclusive option to declare that two clocks are physically active simultaneously, but the two clocks are not actively used at the same time (that is, the clocks are logically mutually exclusive). The physically_exclusive option declares clocks that cannot be physically on the device at the same time.
If you define multiple clocks for the same node, you can use clock group assignments with the logically_exclusive option to declare clocks as mutually exclusive. This technique can be useful for multiplexed clocks.
For example, consider an input port that is clocked by either a 100-MHz or 125-MHz clock. You can use the logically_exclusive option to declare that the clocks are mutually exclusive and eliminate clock transfers between the 100-MHz and 125-MHz clocks, as the following diagrams and example SDC constraints show:
Figure 91. Synchronous Path with Clock Mux Internal to FPGA
Example SDC Constraints for Internal Clock Mux
# Create a clock on each port create_clock -name clk_100 -period 10 [get_ports clkA] create_clock -name clk_125 -period 8 [get_ports clkB] # Create derived clocks on the output of the mux create_generated_clock -name mux_100 -source [get_ports clkA] \ [get_pins clkmux|combout] create_generated_clock -name mux_125 -source [get_ports clkB] \ [get_pins clkmux|combout] -add # Set the two clocks as exclusive clocks set_clock_groups -logically_exclusive -group {mux_100} -group {mux_125}
Figure 92. Synchronous Path with Clock Mux External to FPGA
Example SDC Constraints for External Clock Mux
# Create virtual clocks for the external primary clocks create_clock -period 10 -name clkA create_clock -period 20 -name clkB # Create derived clocks on the port clk create_generated_clock -name mux_100 -master_clock clkA [get_ports clk] create_generated_clock -name mux_125 -master_clock clkB [get_ports clk] -add # Assume no clock network latency between the external clock sources & the \ clock mux output set_clock_latency -source 0 [get_clocks {mux_100 mux_125}] # Set the two clocks as exclusive clocks set_clock_groups -physically_exclusive -group mux_100 -group mux_125