Quartus® Prime Pro Edition User Guide: Design Compilation
ID
683236
Date
7/07/2025
Public
1.1. Compilation Overview
1.2. Design Analysis & Elaboration
1.3. Design Synthesis
1.4. Design Place and Route
1.5. Incremental Optimization Flow
1.6. Fast Forward Compilation Flow
1.7. Full Compilation Flow
1.8. HSSI Dual Simplex IP Generation Flow
1.9. Exporting Compilation Results
1.10. Clearing Compilation Results
1.11. Integrating Other EDA Tools
1.12. Compiler Optimization Techniques
1.13. Compilation Monitoring Mode
1.14. Viewing Quartus Database File Information
1.15. Understanding the Design Netlist Infrastructure
1.16. Using Synopsys* Design Constraint (SDC) on RTL Files
1.17. Using the Node Finder
1.18. Synthesis Language Support
1.19. Synthesis Settings Reference
1.20. Fitter Settings Reference
1.21. Design Compilation Revision History
2.1. Factors Affecting Compilation Results
2.2. Strategies to Reduce the Overall Compilation Time
2.3. Reducing Synthesis Time
2.4. Reducing Placement Time
2.5. Reducing Routing Time
2.6. Reducing Static Timing Analysis Time
2.7. Setting Process Priority
2.8. Reducing Compilation Time Revision History
2.3.1. Using Precompiled Component Generation
Precompiled Component Generation is an optional sub-process of the Analysis & Elaboration stage of compilation. When you enable this sub-process, Precompiled Component Generation partially synthesizes IP components in your design, and stores the compilation results in a project subdirectory called ip_cache. You can use the stored results to reduce synthesis time for those IP in subsequent synthesis runs. Additionally, you can use the stored results created from different projects by you or other developers. Stored results that are accessible for different developers, projects, and machines, are known as shared IP caches.
Leverage Shared IP Caches
Shared IP caches are not necessarily tied to any specific Quartus Prime project. This fact allows you to store and use the partially synthesized IPs across many projects, or many instances of a project on different machines. You can specify multiple shared caches. For multiple shared caches, you must specify the read-order and whether they are read-only or read-write. Any IP that you use from a shared cache copies to the project IP cache during Precompiled Component Generation. New, partially synthesized IPs that you generate locally are copied to the first writeable cache in the list.
The pre-synthesized IP should be synthesized with the same Quartus version as the main project importing itAdvantages of Precompiled Component Generation
- Each unique IP generates only once and is cached. Unless you modify any of the IP in your design, any subsequent synthesis run does not perform Precompiled Component Generation.
- If you modify any IP in the design, Precompiled Component Generation performs only on the modified IP.
- Precompiled Component Generation occurs in parallel for each IP.
- Synthesis time savings scales with the proportion of the design that is IP.
Precompiled Component Generation does the following:
- Partially synthesizes IP components in your design.
- Generates and stores IP synthesis results in your project's ip_cache directory and in any writable, shared IP cache that you specify.
Note: It is best to create any shared IP caches in the parent directory.
- Reuses the cached IP components in subsequent synthesis runs.
Figure 136. Precompiled Component Generation Flow