Quartus® Prime Pro Edition User Guide: Design Compilation
ID
683236
Date
7/07/2025
Public
1.1. Compilation Overview
1.2. Design Analysis & Elaboration
1.3. Design Synthesis
1.4. Design Place and Route
1.5. Incremental Optimization Flow
1.6. Fast Forward Compilation Flow
1.7. Full Compilation Flow
1.8. HSSI Dual Simplex IP Generation Flow
1.9. Exporting Compilation Results
1.10. Clearing Compilation Results
1.11. Integrating Other EDA Tools
1.12. Compiler Optimization Techniques
1.13. Compilation Monitoring Mode
1.14. Viewing Quartus Database File Information
1.15. Understanding the Design Netlist Infrastructure
1.16. Using Synopsys* Design Constraint (SDC) on RTL Files
1.17. Using the Node Finder
1.18. Synthesis Language Support
1.19. Synthesis Settings Reference
1.20. Fitter Settings Reference
1.21. Design Compilation Revision History
2.1. Factors Affecting Compilation Results
2.2. Strategies to Reduce the Overall Compilation Time
2.3. Reducing Synthesis Time
2.4. Reducing Placement Time
2.5. Reducing Routing Time
2.6. Reducing Static Timing Analysis Time
2.7. Setting Process Priority
2.8. Reducing Compilation Time Revision History
1.16.4.1.2. SDC-on RTL Example: Targeting Pins in Cells
When constraining your design, you might need to target cell pins to apply constraints. In such scenarios, you can use the get_pins Tcl command and RTL names to locate specific cell pins, such as clk or d inputs and q outputs. For example:
get_pins U5|reg_a[0]|clk get_pins U5|reg_a[0]|d get_pins U7|rega_a[0][0]|q
Figure 122. Targeting Pins in Cells Diagram
These Tcl commands return specific pins of the reg_a[0] register in the U5 instance. You can use the returned collection to constrain paths. For example, from U5|reg_a[0] to U7|rega_a[0][0] as follows:
set_false_path -from [get_pins U5|reg_a[0]|clk] -to [get_pins U7|rega_a[0][0]|d]