AN 802: Intel® Stratix® 10 SoC Device Design Guidelines
ID
683117
Date
8/05/2021
Public
1. Introduction to the Intel® Stratix® 10 SoC Device Design Guidelines
2. Board Design Guidelines for Stratix 10 SoC FPGAs
3. Interfacing to the FPGA for Stratix 10 SoC FPGAs
4. System Considerations for Stratix 10 SoC FPGAs
5. Embedded Software Design Guidelines for Intel® Stratix® 10 SoC FPGAs
6. Recommended Resources for Stratix 10 SoC FPGAs
2.1. Pin Connection Considerations for Board Design
2.2. HPS Clocking and Reset Design Considerations
2.3. Design Considerations for Connecting Device I/O to HPS Peripherals and Memory
2.4. Design Guidelines for HPS Interfaces
2.5. HPS EMIF Design Considerations
2.6. HPS Memory Debug
2.7. Boundary Scan for HPS
2.8. Embedded Software Debugging and Trace
2.9. Board Design Guidelines for Intel® Stratix® 10 SoC FPGAs Revision History
3.1. Overview of HPS Memory-Mapped Interfaces
3.2. Recommended System Topologies
3.3. Recommended Starting Point for HPS-to-FPGA Interface Designs
3.4. Timing Closure for FPGA Accelerators
3.5. Information on How to Configure and Use the Bridges
3.6. Interfacing to the FPGA for Intel® Stratix® 10 SoC FPGAs Revision History
5.1. Overview
5.2. Assembling the Components of Your Software Development Platform
5.3. Golden Hardware Reference Design (GHRD)
5.4. Selecting an Operating System for Your Application
5.5. Assembling Your Software Development Platform for Linux*
5.6. Assembling your Software Development Platform for a Bare-Metal Application
5.7. Assembling your Software Development Platform for Partner OS or RTOS
5.8. Choosing the Bootloader Software
5.9. Selecting Software Tools for Development, Debug and Trace
5.10. Boot And Configuration Considerations
5.11. System Reset Considerations
5.12. Flash Considerations
5.13. Embedded Software Debugging and Trace
5.14. Embedded Software Design Guidelines for Intel® Stratix® 10 SoC FPGAs Revision History
3.1.4. FPGA-to-SDRAM Ports
GUIDELINE: Use the FPGA-to-SDRAM ports for non-cacheable access to the HPS SDRAM from masters in the FPGA.
The FPGA-to-SDRAM ports allow masters implemented in the FPGA fabric to directly access HPS SDRAM without the transactions flowing through the CCU. There are three FPGA-to-SDRAM ports—FPGA-to-SDRAM0, FPGA-to-SDRAM1, FPGA-to-SDRAM2—supporting 32-, 64-, or 128-bit data paths. These interfaces connect only to the HPS SDRAM subsystem so Intel® recommends to use them in your design if the FPGA needs high-throughput, low-latency access to the HPS SDRAM. The exception to this recommendation is if the FPGA requires cache coherent access to use the FPGA-to-HPS bridge with support for cache coherent accesses using the ACE-Lite protocol.