JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide
ID
683113
Date
10/14/2022
Public
1.2.1. Features
This design example has the following key features:
- Control mechanisms:
- System Console using Tcl script control mechanism
- Nios II soft processor using embedded C code
- Synthesis and simulation flows—Nios II soft processor control design only supports synthesis flow
- Configurable transport layer and pattern generator and checker modules
- Power-on self test with the following configurable test patterns:
- Alternating
- Ramp
- PRBS
- Supports simplex (RX only, TX only) and duplex (both RX and TX) data path modes
- Supports transceiver dynamic reconfiguration mode
- Supports option for 3-wire SPI