JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

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ID 683113
Date 10/14/2022
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Arria® 10 FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide Document Archives 1.4. Document Revision History for the JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide
1.1. JESD204B Intel® Arria® 10 FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Hardware Test for System Console Control Design Example 1.1.4.2. Hardware Test for Nios Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Functional Description 1.2.6. Simulation 1.2.7. Design Example Files 1.2.8. Registers 1.2.9. Signals 1.2.10. Software Control Flow 1.2.11. Customizing the Design Example
1.2.5. Functional Description x
1.2.5.1. Design Components 1.2.5.2. Clocking Scheme
1.2.5.1. Design Components x
1.2.5.1.1. Platform Designer System Component 1.2.5.1.2. Transport Layer 1.2.5.1.3. Test Pattern Generator 1.2.5.1.4. Test Pattern Checker
1.2.5.1.1. Platform Designer System Component x
1.2.5.1.1.1. JESD204B Subsystem in Platform Designer 1.2.5.1.1.2. Parallel I/O 1.2.5.1.1.3. ATX PLL 1.2.5.1.1.4. Core PLL 1.2.5.1.1.5. SPI Master 1.2.5.1.1.6. Nios Subsystem
1.2.6. Simulation x
1.2.6.1. Testbench
1.2.10. Software Control Flow x
1.2.10.1. Software Parameters 1.2.10.2. Interrupt Service Routines (ISR) 1.2.10.3. Software Functions Description
1.2.10.3. Software Functions Description x
1.2.10.3.1. Functions in main.c Source File 1.2.10.3.2. Custom Peripheral Access Macros in macros.c Source File
1.2.11. Customizing the Design Example x
1.2.11.1. Modifying the JESD204B IP Core Parameters 1.2.11.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

1.4. Document Revision History for the JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.09.16 21.3 19.2.0
  • Added Table: Supported JESD204B IP Parameter Configurations (L, M, F Values)
2021.11.01 21.3 19.2.0 Updated the JESD204B Intel® Arria® 10 FPGA IP Design Example Quick Start Guide chapter:
  • Added support for QuestaSim* simulator.
  • Removed references to the NCSim simulator.
2020.02.13 17.1 17.1
  • Updated Table: Parameters in the Example Design Tab.
  • Updated information about duplex variant in the ATX PLL section.
  • Updated for latest branding standards.
  • Renamed the document as JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide.
Date Version Changes
November 2017 2017.11.06
  • Added information about simplex and duplex ATX reference clock frequencies.
  • Defined (altera_jesd204_ed_<data path>.sv) as the top level RTL file in Core PLL.
  • Added Frame Clock and Link Clock Relationship subsection.
  • Defined top level RTL file in Changing the Data Rate or Reference Clock Frequency.
  • Updated SDC constraint to be modified in Changing the Data Rate or Reference Clock Frequency.
  • Added get_master_index procedure in Procedures in the main.tcl System Console Script table.
  • Updated document title.
  • Updated instances of Qsys to Platform Designer.
  • Added note to System Clocking for the Design Example table about additional jitter introduced to the ATX, fPLL, and transmit PLL output when using reference clock from a cascaded PLL output, global clock or core clock network.
May 2017 2017.05.08 Initial release.
Level Two Title