E-Tile JESD204C Intel® FPGA IP User Guide

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ID 683108
Date 1/26/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the E-Tile JESD204C Intel FPGA IP User Guide 2. Overview of the JESD204C Intel FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the JESD204C Intel® FPGA IP 6. JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. E-Tile JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the E-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the JESD204C Intel FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. JESD204C Intel® FPGA IP Features 2.4. Presets 2.5. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. JESD204C IP Component Files 4.5. Creating a New Intel® Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the JESD204C Intel® FPGA IP x
5.1. JESD204C TX and RX Reset Sequence 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Deterministic Latency
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter Registers 8.2. Receiver Registers
1. About the E-Tile JESD204C Intel FPGA IP User Guide
2. Overview of the JESD204C Intel FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the JESD204C Intel® FPGA IP
6. JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. E-Tile JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the E-Tile JESD204C Intel® FPGA IP User Guide

2.3. JESD204C Intel® FPGA IP Features

The JESD204C Intel® FPGA IP is a high-speed point-to-point serial interface intellectual property (IP). The JESD204C Intel® FPGA IP is the latest IP from Intel that supports the JESD204C protocol. This IP is not backwards compatible and does not support JESD204B protocol. You can use the existing the JESD204B Intel® FPGA IP to support JESD204B protocol.

Table 7.  Brief Information about the JESD204C Intel® FPGA IP

Features

Description

Protocol Features

  • Joint Electron Device Engineering Council (JEDEC) JESD204C standard 2017
  • Device subclass:
    • Subclass 0—No deterministic latency.
    • Subclass 1—Uses SYSREF signal to support deterministic latency

Core Features

  • Data rate of up to 28.9 Gbps for Intel Agilex® 7 and Intel® Stratix® 10 (E-tile) devices.
  • Single or multiple lanes (up to 16 lanes per link)
  • Local extended multiblock clock (LEMC) counter based on E=1 to 256
  • Serial lane alignment and monitoring
  • Lane synchronization
  • Modular design that supports multidevice synchronization
  • MAC and PHY partitioning
  • Deterministic latency support
  • 64/66 encoding
  • Scrambling/descrambling
  • Avalon® streaming interface for transmit and receive datapaths
  • Avalon® memory-mapped interface for control and status registers (CSR)
  • Dynamic generation of simulation testbench
  • Optional support for ECC M20K DCFIFO
  • Options for sync header configurations
    • CRC-12
    • Standalone command channels
Limitations No FEC support

Typical Application

  • Wireless communication equipment
  • Broadcast equipment
  • Military equipment
  • Medical equipment
  • Test and measurement equipment

Device Family Support

  • Intel Agilex® 7 and Intel® Stratix® 10 (E-tile) FPGA devices

Design Tools

  • Platform Designer parameter editor in the Intel® Quartus® Prime Pro Edition software for design creation and compilation

  • Timing Analyzer in the Intel® Quartus® Prime software for timing analysis

  • ModelSim* - Intel® FPGA Starter Edition, QuestaSim* simulator, VCS* / VCS* MX, and Xcelium* Parallel simulator software for design simulation or synthesis
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