Nios® V Processor Intel® FPGA IP Release Notes

ID 683098
Date 5/22/2025
Public
Document Table of Contents

5.1. Nios® V/g Processor Intel® FPGA IP v4.0.0

Table 23.  v4.0.0 2025.03.17
Quartus® Prime Version Description Impact
24.1std
  • Removed Atomic extension.
  • Updated Instruction and Data TCM to true dual port memories. This removes the requirement of "WFI" to access [I/D]TCS AXI4 lite interfaces.
  • Fixed minor warnings.
  • Introduced branch prediction module into the processor.
  • Added single-bit correction feature in the Error Correction Code (ECC) module.
  • Added Lockstep feature.
  • Added optional cache feature.
  • Added CLINT-Vectored mode.
  • Added optional FSQRT and FDIV instruction for Floating-Point Unit (FPU).
  • Added Shadow Register File and Core-Local Interrupt Controller (CLIC).
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