Quartus® Prime Pro Edition User Guide: Design Recommendations
ID
683082
Date
4/14/2025
Public
1.1. Using Provided HDL Templates
1.2. Instantiating IP Cores in HDL
1.3. Inferring Multipliers and DSP Functions
1.4. Inferring Memory Functions from HDL Code
1.5. Register and Latch Coding Guidelines
1.6. General Coding Guidelines
1.7. Designing with Low-Level Primitives
1.8. Cross-Module Referencing (XMR) in HDL Code
1.9. Using force Statements in HDL Code
1.10. Recommended HDL Coding Styles Revision History
1.4.1.1. Use Synchronous Memory Blocks
1.4.1.2. Avoid Unsupported Reset and Control Conditions
1.4.1.3. Check Read-During-Write Behavior
1.4.1.4. Controlling RAM Inference and Implementation
1.4.1.5. Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior
1.4.1.6. Single-Clock Synchronous RAM with New Data Read-During-Write Behavior
1.4.1.7. Simple Dual-Port, Dual-Clock Synchronous RAM
1.4.1.8. True Dual-Port Synchronous RAM
1.4.1.9. Mixed-Width Dual-Port RAM
1.4.1.10. Inferring RAM with Byte-Enable Signals
1.4.1.11. Inferring Simple Quad-Port RAM
1.4.1.12. Specifying Initial Memory Contents at Power-Up
1.6.6.1. If Performance is Important, Optimize for Speed
1.6.6.2. Use Separate CRC Blocks Instead of Cascaded Stages
1.6.6.3. Use Separate CRC Blocks Instead of Allowing Blocks to Merge
1.6.6.4. Take Advantage of Latency if Available
1.6.6.5. Save Power by Disabling CRC Blocks When Not in Use
1.6.6.6. Initialize the Device with the Synchronous Load (sload) Signal
3.4.1. Apply Complete System-Centric Timing Constraints for the Timing Analyzer
3.4.2. Force the Identification of Synchronization Registers
3.4.3. Set the Synchronizer Data Toggle Rate
3.4.4. Optimize Metastability During Fitting
3.4.5. Increase the Length of Synchronizers to Protect and Optimize
3.4.6. Increase the Number of Stages Used in Synchronizers
3.4.7. Select a Faster Speed Grade Device
3.4.3. Set the Synchronizer Data Toggle Rate
The MTBF calculations assume the data being synchronized is switching at a toggle rate of 12.5% of the source clock frequency.
To help ensure accurate MTBF analysis for reset synchronizers, specify the toggle_rate for all reset synchronizers in your design. If you know an approximate rate at which the data changes, you can specify this with the Synchronizer Toggle Rate logic option assignment in the Assignment Editor.
Note: Starting in Quartus® Prime Pro Edition software version 25.1, the Synchronizer Toggle Rate logic option assignment is now double type (rather than integer), allowing input of decimal values.
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