1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Release Notes

ID 683019
Date 11/16/2023
Public

1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP v19.1

Table 5.  v19.1 April 2019
Description Impact
Renamed the Enable Altera Debug Master Endpoint parameter to Enable Native PHY Debug Master Endpoint as per Intel® rebranding in the Intel® Quartus® Prime Pro Edition software. The Intel® Quartus® Prime Standard Edition software still uses Enable Altera Debug Master Endpoint.