Intel® Intrinsics Guide

 
Updated                 Version
08/10/2022           3.6.3

Instruction Set
MMX
SSE
SSE2
SSE3
SSSE3
SSE4.1
SSE4.2
AVX
AVX2
FMA
AVX_VNNI
AVX-512
KNC
AMX
SVML
Other

Categories


All throughput and latency data is sourced from Intel® 64 and IA-32 Architectures Software Developer Manuals .

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This intrinsic generates a sequence of instructions, which may perform worse than a native instruction. Consider the performance impact of this intrinsic.