Spatial DPC++ Constructs for Algorithm Acceleration with FPGAs

Get an overview of spatial language constructs exposed in SYCL* and Data Parallel C++ (DPC++) and how to work with them. Specifically, this talk describes the parallel running of kernels with pairwise independent forward progress and the variety of communication mechanisms enabled by the pipes features. Learn about memory-system tuning controls and the recommended report-driven methodology for development. Get started adapting algorithms for spatial accelerator implementation, both initially and for optimization.

Mike Kinsner is a principal engineer at Intel where he develops languages and parallel-programming models for a variety of compute architectures. He is one of the architects of DPC++. He started his career at Altera, working on high-level synthesis for field-programmable gate arrays (FPGAs) and still contributes to spatial-programming models and compilers. He is an Intel representative within the Khronos* Group standards organization, where he works on the SYCL and OpenCL™ standard for parallel programming. He holds a PhD in computer engineering from McMaster University and recently coauthored the industry’s first book on SYCL and DPC++.

Product and Performance Information

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Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.