The Advanced Programmable Interrupt Controller (APIC) is an integrated CPU component responsible for accepting, prioritizing, and dispatching interrupts to logical processors (LPs).
The APIC architecture, which was introduced in Pentium 4 processors, is now referred to as the xAPIC architecture. The second generation of APIC architecture, x2APIC, which is an extension of the xAPIC architecture, was introduced in Intel® microarchitecture code name Nehalem for Intel® Core™ i-series processors. Refer to Volume 3A, chapter 11 ”Advanced Programmable Interrupt Controller,” Intel® 64 and IA-32 Architectures Software Developer’s Manuals.
X2APIC is a requirement for any processors that have core counts greater than 255.
This technical paper describes how native support for xAPIC will be gradually deprecated. Note that xAPIC can continue to be virtualized for guests with the support of the VMM. There are no immediate plans to deprecate the APIC virtualization features that help efficiently virtualize guest xAPIC usage. Refer to Volume 3A, chapter 31 ”APIC Virtualization and Virtual Interrupts” Intel® 64 and IA-32 Architectures Software Developer’s Manuals.
BIOS vendors and OEMs should inform your Intel representative when changing the default x2APIC configuration back to xAPIC. To avoid problems, when xAPIC is deprecated, it is not recommended for custom BIOS to enable xAPIC.
Progression to Deprecate xAPIC
xAPIC will be deprecated in a phased approach defined by processor family. During certain deprecation phases, shown in the table below, some processors may still support xAPIC. Legacy support is defined as all the processors before Intel® Core™ Ultra processors code named Meteor Lake, where xAPIC is supported as the default. For processors released starting with and after Meteor Lake, x2APIC is the default, and returning to xAPIC mode is not recommended.
| Deprecation phase | Processor family | xAPIC behavior | X2APIC behavior | Reference BIOS behavior | |
|---|---|---|---|---|---|
|
0 |
Legacy - Processors before Intel® Core™ Ultra processors code named Meteor Lake |
Default |
Supported |
By default, reference BIOS hands off to the operating system in xAPIC mode. The OS may switch to x2APIC mode, and may return to xAPIC mode after a reboot (either with a cold or warm reset). However, the reference or custom BIOS may be configured to enable x2APIC prior to OS handoff. | |
|
1 |
x2APIC -Client: Intel® Core™ Ultra processors code named Meteor Lake |
Supported via manual configuration of the BIOS or OS. |
Default |
Reference BIOS hands off to the operating system in x2APIC mode by default. The OS starts in x2APIC mode unless the reference BIOS is manually configured to xAPIC or a custom BIOS configured to xAPIC is used. The OS can switch from x2APIC mode back to xAPIC mode. | |
|
2a |
Client: Intel Core Ultra processors code named Lunar Lake and Arrow Lake (which do not have Intel SGX or Intel TDX functionality) |
Supported via manual configuration of the BIOS only. |
Default, one-way |
Reference BIOS hands off to the operating system in x2APIC mode by default. The OS starts in x2APIC mode and cannot switch from x2APIC mode back to xAPIC mode. This is because the processors enumerates IA32_ARCH_CAPABILITIES[21](XAPIC_DISABLE_STATUS) as 1 and IA32_XAPIC_DISABLE_STATUS[0] as 1. Thus, switching to xAPIC mode requires a reboot and manual configuration of the BIOS. | |
|
2b |
Client: Intel Core Ultra processors code named Panther Lake and Wildcat Lake Server: Intel Xeon processors code named Sapphire Rapids and Emerald Rapids |
Supported via manual configuration for platforms without Intel SGX or Intel TDX only. |
Default, one-way (required for Intel SGX and Intel TDX) |
Reference BIOS hands off to the operating system in x2APIC mode by default. Once in x2APIC mode, the OS cannot return to xAPIC mode even after a reboot (either with a cold or warm reset) unless the reference or custom BIOS is manually reconfigured to xAPIC. Intel SGX and TDX require x2APIC mode to be enabled. This is because the processor enumerates IA32_ARCH_CAPABILITIES[21](XAPIC_DISABLE_STATUS) as 1 and IA32_XAPIC_DISABLE_STATUS[0] as 1. | |
|
3 |
Server: Intel Xeon processors code named Granite Rapids and Sierra Forest |
Not supported |
Default on all server processors |
The reference BIOS no longer supports xAPIC and it hands off to the operating system in x2APIC mode. Once in x2APIC mode, the OS cannot return to xAPIC mode. It is not recommended for custom BIOS to support disabling x2APIC mode. | |
|
4 |
Client: Intel Core Ultra processors code named Nova Lake and later Server: Intel Xeon processors code named Diamond Rapids and later |
Deprecated—xAPIC no longer supported in the processor. |
Default on all processors |
Processors do not have support for xAPIC. |
References
- Alder Lake Processor External Design Specification (EDS), Volume 1 of 2
- Raptor Lake and Raptor Lake Refresh Processors External Design Specification (EDS), Volume 1 of 2
- Intel® Core™ Ultra Processor External Design Specification (EDS), Volume 1 of 2
- Arrow Lake-S and Arrow Lake-HX Processor External Design Specification, Volume 1 of 2
- Arrow Lake-H/U Processor External Design Specification
- Lunar Lake-MX Processor External Design Specification (EDS), Volume 1 of 2
- Panther Lake U/H Processor External Design Specification, Volume 1 of 2
- Wildcat Lake Processor External Design Specification, Volume 1 of 2