Introduction to the Intel® Resource Director Technology Features in Intel® Xeon® Processors E5 v4

Published: 03/29/2016  

Last Updated: 03/29/2016

By Khang T Nguyen

Introduction

The Intel® Xeon® processor E5 v4 family of server processors introduces advanced new resource monitoring and control features designed to improve visibility into and control over how shared platform resources such as the L3 cache are used.

The Cache Monitoring Technology (CMT) feature in the Intel® Xeon® processor E5 v3 provides a starting point with improved visibility of how the L3 cache is used by threads, apps, virtual machines (VMs) or containers, and the new Intel® Resource Director Technology (Intel® RDT) feature set extends these capabilities substantially.

More information on the Intel RDT feature set can be found here.

An animation illustrating the key principles behind Intel RDT is posted here.

Key Intel Resource Director Technology Features on the Intel® Xeon® Processor E5 v4 Family:

  • Cache Allocation Technology (CAT)

Formerly available on a limited subset of Intel Xeon processor E5 v3 communications SKUs, an enhanced version of CAT is now available across all Intel Xeon processor E5 v4 SKUs. CAT enables software control over the placement of data in the L3 cache, enabling new usages including prioritizing important VMs in the data center, containing “noisy neighbors,” and protecting important communications applications, such as virtual switches, from interference.

CAT is a feature that enables an OS, hypervisor / virtual machine manager (VMM) or similar system service management agent to specify the amount of cache space into which an application can fill. This technology provides control over last level cache (LLC) allocation. 

Why is there a need to specify a certain amount of cache space that an application can use in LLC? When multiple applications are running concurrently, they will compete with each other for cache space. An application such as video streaming that requests a large chunk of data but never reuses that data does not necessarily use the cache well (low temporal locality), meaning LLC space is used that could otherwise be used to improve the performance of other applications or VMs.

In such cases, operators can use CAT to limit how much cache space the video streaming application can use, leaving cache space available for more important applications to use. Such prioritization is one key usage of CAT, and others are possible as described in a series of articles:

  • Memory Bandwidth Monitoring (MBM)

Multi-core cache hierarchies benefit applications with substantial throughput and scalability. However, when many user processes are running concurrently, cache and memory bandwidth are frequently contended resources and must be monitored and used efficiently to achieve the best performance.

MBM allows monitoring of bandwidth from one level of the cache hierarchy to the next—in this case focusing on the L3 cache. The architecture is based on an extension of the existing Cache Monitoring Technology (CMT) feature, which uses per-thread tags, meaning that per-thread bandwidth can be measured for applications, VMs, or containers. Additionally, bandwidth to both local and remote memory controllers is provided (via local/total event codes), meaning bandwidth-aware scheduling and NUMA optimizations are possible.

More information about MBM can be found in a series of articles:

  • Code and Data Prioritization (CDP)

Certain applications with large code footprints, or those with above-average sensitivity to protecting code in the cache may benefit from the software control provided by Code and Data Prioritization (CDP), which is an extension of CAT. CDP enables isolation and separate prioritization of code and data placement in the LLC in a software configurable manner, which can enable workload tuning of cache capacity to the characteristics of the workload.

More information about CDP is available in a series of articles:

 

Conclusion

The Intel RDT feature set enables improved monitoring of L3 cache occupancy and memory bandwidth, while providing new levels of control over the way that applications make use of the L3 cache. Enhanced capabilities are possible using these features, including improved telemetry, resource-aware scheduling, improved performance guarantees, and enhanced fairness and determinism. The articles referenced above provide additional details on the capabilities available.

 

Notices

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Product and Performance Information

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Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.