This document provides a summary of new and changed features of the Intel® C++ Compiler for applications running on Embedded Linux* and Android* targets. It also includes notes about features and problems not described in the product documentation.
Please see the licenses included in the distribution as well as the Disclaimer and Legal Information section of these release notes for details. Please see the following links for information on this release of the Intel® C++ Compiler 18.0.
Changes in Update 2 (Intel® C++ Compiler 18.0.4)
- Changes to mitigate speculative executive side channel issue and new -mconditional-branch option. Please see detailed article at Using Intel® Compilers to Mitigate Speculative Execution Side-Channel Issues available at /content/www/us/en/develop/articles/using-intel-compilers-to-mitigate-speculative-execution-side-channel-issues.html
- __INTEL_LIBIRC_DEBUG environment variable
- Restored context sensitive help in VS
- /Q[a]xIcelake-server and /Q[a]xIcelake-client options added to support Ice Lake microarchitecture
- /Q[a]xCannonlake option added to support Cannon Lake microarchitecture
- Corrections to reported problems
Changes in Update 1 (Intel® C++ Compiler 18.0.2)
- Deprecated “Enable C++11 support (/Qstd=c++11)” and “Enable C99 support (/Qstd=c++11)” properties in all supported VS versions (VS2017, VS2015, VS2013)
- Changes to mitigate Spectre variant 2 issue and new -mindirect-branch option. Please see detailed article at Using Intel® Compilers to Mitigate Speculative Execution Side-Channel Issues available at /content/www/us/en/develop/articles/using-intel-compilers-to-mitigate-speculative-execution-side-channel-issues.html
- Fixes for reported problems
Changes since Intel® C++ Compiler 17.0 (New in Intel® C++ Compiler 18.0)
- CET - Control-Flow Enforcement Technology support
- New option -Qimf-use-svml to enforce SVML
- Compile time dispatching for SVML calls
- Support for the Intel® Xeon Phi™ x100 product family coprocessor (formerly code name Knights Corner) is removed in this release
- All -o* options replaced with -qo* options
- Parallel STL for parallel and vector execution of the C++ STL
- Support of hardware based PGO
- monotonic and overlap keywords for an ordered block in simd context
- Change in behavior of extract ( _mm256_extract_epi8 ) intrinsics return type
- Features from OpenMP* TR4 Version 5.0 Preview 1
- Support for more new features in OpenMP* 4.0 or later
- New C++17 features supported
- Adding support for atomic keyword in C11 features
- New and changed compiler options
- 32-bit icc wrapper deprecated in 18.0
- Intel® Cilk™ Plus deprecated in 18.0
- Offline documentation removed from the Installed image
- New /Qopt-zmm-usage
- Correction to reported problems
For an explanation of architecture names, see http://intel.ly/q9JVjE
- A PC based on Intel® 64 architecture processor supporting the Intel® Streaming SIMD Extensions 2 (Intel® SSE2) instructions (Intel® 2nd Generation or newer Generation of Intel® Core™ i3, i5, or i7 processors and Intel® Xeon® E3 or E5 processor family, or compatible non-Intel processor).
- Development of 32-bit applications is now supported on a 64-bit version of the OS only. The compiler cannot be installed on a 32-bit OS.
- For the best experience, a multi-core or multi-processor system is recommended
- 2GB of RAM (4GB recommended)
- 7.5GB free disk space for all features
- Microsoft Windows 7* (SP1), Microsoft Windows 8*, Microsoft Windows 8.1* or Windows 10*
- The prerequisite for successful Wind River* Linux* targeted cross-build environment integration is
- Wind River* Workbench for Wind River* Linux* 7.x - 8.x
- The prerequisite for successful Android* targeted cross-build environment integration is
- Android* NDK version r13, r13b, r14, r14b, r15, r15b, r15c or r16
- Android* Open Source Project (AOSP) workspace, for example, AOSP workspace for Android 6.0, Android 7.0 or Android 8.0
- To read the on-disk documentation, Adobe Reader* 7.0 or later
- The default for the Intel® compilers is to build IA-32 architecture applications that require a processor supporting the Intel® SSE2 instructions - for example, the Intel® Pentium® 4 processor. A compiler option is available to generate code that will run on any IA-32 architecture processor. However, if your application uses Intel® Integrated Performance Primitives or Intel® Threading Building Blocks, executing the application will require a processor supporting the Intel® SSE2 instructions.
- Compiling very large source files (several thousands of lines) using advanced optimizations such as -O3 or -ipo may require substantially larger amounts of RAM.
- The above lists of processor model names are not exhaustive - other processor models correctly supporting the same instruction set as those listed are expected to work. Please refer to Technical Support if you have questions regarding a specific processor model.
- Some optimization options have restrictions regarding the processor type on which the application is run. Please see the documentation of these options for more information.
- Development platform based on the Intel® Atom™ processor Z5xx, N4xx, N5xx, D5xx E6xx, N2xxx, D2xxx, Z3xxx, E3xxx, C2xxx, the Intel® Atom™ processor CE4xxx, CE53xx or the Intel® Puma6™ Media Gateway.
- Alternatively, development platform based on 2nd, 3rd or 4th generation Intel® Core™ microarchitecture based Intel® Core™ processor or Intel® Xeon™ processor.
- Development targeting Intel® Quark processor X1xxx
- Needed hard disk space
- IA-32: 13 MB
- Intel 64: 15 MB
The target platform should be based on one of the following environments:
- Yocto Project* 1.7, 1.8, 1.9, 2.0, 2.2 based environment
- Wind River* Linux* 7, 8, 9 based environment
- openSUSE* 13.2
- Tizen* IVI 2.0, 3.0
- Android 7 Nougat for both IA-32 and Intel® 64
- Android 6.0 Mashmallow for both IA-32 and Intel® 64
Intel System Studio 2018: Getting Started with the Intel® C++ Compiler 18.0* at <install-dir>\documentation_2018\en\compiler_c\iss2018\l_a_compiler_get_started.htm contains information on how to use the Intel® C++ Compiler from the command line and from Eclypse*.
The Intel® C++ Compiler for Linux* does not provide "modulefiles" for usage with the Environmental Modules software utility but is well suited for such usage. See Using Environment Modules with Intel Development Tools for further information.
Product documentation is linked from <install-dir>\documentation_2018\en\compiler_c\. Full documentation for all tool components is available at the Intel System Studio Documentation page.
Offline core documentation is removed from the Intel® System Studio installed image. The core documentation for the components of Intel® System Studio is available at the Intel® Software Documentation Library for viewing online. You can also download an offline version of the documentation from the Intel® Software Development Products Registration Center: Product List > Intel® System Studio Documentation.
- Please see Intel® System Debugger Support Resources for further information.
Product samples are now available online at Intel® Software Product Samples and Tutorials.
If you did not register your compiler during installation, please do so at the Intel® Software Development Products Registration Center at https://lemcenter.intel.com. Registration entitles you to free technical support, product updates, and upgrades for the duration of the support term.
For information about how to find Technical Support, Product Updates, User Forums, FAQs, tips and tricks, and other support information, please visit: http://www.intel.com/software/products/support/
Note: If your distributor provides technical support for this product, please contact them for support rather than Intel.
The following features are new or significantly enhanced in this version. For more information on these features, please refer to the documentation.
New keywords for existing
#pragma omp ordered simd
#pragma omp ordered simd monotonic()
#pragma omp ordered simd overlap(expr)
#pragma omp simd reduction(=: list)
Please refer the Intel® C++ Compiler 18.0 User and Reference Guide for more details
Profile Guided Optimization (PGO) Hardware-based event sampling is a new low overhead model to get (many) benefits of PGO using the Intel® Compiler and the Intel® VTune™ Amplifier. Data collection works on systems where Intel® VTune™ Amplifier is supported.
Please refer the Intel® C++ Compiler 18.0 User and Reference Guide for more details
Intel(R) C++ Compiler is installed with Parallel STL, an implementation of the C++ standard library algorithms with support for execution policies.
To learn more, please refer to article https://software.intel.com/en-us/get-started-with-pstl
Intel defined 256-bit vector intrinsics
_m256_extract_epi8/epi16(__m256i a, const int index) return int instead of __int8/__int16 values.
New option forces use of SVML where currently LIBM is used, for scalar math. This guarantees the bitwise-same result of computations made with vectorized code vs computations made with scalar code. With this feature, the compiler vectorizes math functions in /fp:precise FP model and vectorized code produce results consistent with scalar code results.
Control-flow Enforcement Technology (CET) defends a program from certain attacks that exploit vulnerabilities, e.g. Return-oriented Programming (ROP) and similarly Call/Jmp-oriented Programming (COP/JOP). Please refer to the Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 1: Basic Architecture for more details.
New compiler option /Qcf-potection[:keyword] introduced in the compiler to support CET.
The compiler default behaviour is changed for SVML functions and a call to cpu-specific SVML entry is performed. Specifying new option -Qimf-force-dynamic-target reverts to the previous behavior and dynamic SVML dispatching is used.
Language features for task reductions from the OpenMP* Technical Report 4: Version 5.0 Preview 1 specifications are now supported.
- TASKGROUP now has the TASK_REDUCTION clause.
- TASK includes now has the IN_REDUCTION clause
- TASKLOOP now has the REDUCTION and IN_REDUCTION clauses
For more information, see the compiler documentation or the link to the OpenMP* Specification above.
- taskloop construct feature
#pragma omp taskloop[clause[[,]clause]..]
- Support for #pragma omp for linear (list [ : linear-step ])
- where list is either list or modifier(list)
- Support for ref, val, and uval modifiers for the linear clause
- Examples: linear(ref(p)), linear(val(i):1), linear(uval(j):1)
- Support for #pragma omp simd simdlen(n)
- Support for #pragma omp ordered [simd]
- Reductions over whole arrays: int x[n]; #pragma omp simd reduction(+:x)
- Intel® processor clause extension added to #pragma omp declare simd (proposed; not officially part of OpenMP* 4.5)
- support for clauses
#pragma omp for schedule :
- The Intel® C++ Compiler 17.0 include
NONMONOTONICmodifiers extension to schedule clause to enhance user control of how iterations of the for loop are divided among threads of the team. See the Intel® C++ Compiler User’s Guide for more details.
- The Intel® C++ Compiler 17.0 include
- support for array sections as list items in the reduction clause
reduction(reduction-identifier:list)If a list item is an array section, it is treated as if reduction clause is applied to each separate element of the section. The elements of the private array sections will be allocated contiguously
The Intel® C++ Compiler 18.0 supports the following features under the /Qstd=c++17 (Windows*) or -std=c++17 (Linux*/macOS*) options:
- Static assert with no message (N3928)
- Relaxed Range based for loops ()
- Please see C++17 Features Supported by Intel® C++ Compiler for an up-to-date listing of all supported features, including comparisons to previous major versions of the compiler.
The Intel® C++ Compiler supports the C11 features under the /Qstd=c11 (Windows*) or -std=c11 (Linux*/macOS*) options:
- Support for all C11 features including C11 keyword _Atomic and __attribute((atomic))
- Please see C11 Support in Intel® C++ Compiler for an up-to-date listing of all supported features, including comparisons to previous major versions of the compiler.
You can tune the zmm code generation done by the compiler with the new additional option -qopt-zmm-usage:low|high. The argument value of low provides a smooth transition experience from - Intel® Advanced Vector Extensions 2 (Intel® AVX2) ISA to Intel® Advanced Vector Extensions 512 (Intel® AVX-512) ISA on a Intel® Xeon® Platinum processor (formerly code name Skylake), such as for enterprise applications. Tuning for ZMM instruction use via explicit vector syntax such as #pragma omp simd simdlen() is recommended. The argument value of high is recommended for applications, such as HPC codes, that are bounded by vector computation to achieve more compute per instruction through use of the wider vector operations. The default value is low for Skylake server microarchitecture-family compilation targets and high for Intel® Core™ /Intel® Many Integrated Core Architecture (Intel® MIC Architecture) Intel® AVX-512 combined compilation targets.
All –o* options replaced by –qo* options
All the –o* options deprecated in the previous release have been replaced with –qo* options in this release with one exception. There is no change to the –o option for Linux* and macOS* used to name the output file.
On Windows*, this change impacts compiler options passed to the target compilation with the /Qoffload-option Compiler option.
A new diagnostic is issued when any now replaced –o option is used. For example:
$ icc -openmp example.c
icc: command line error: option '-openmp' is not supported. Please use the replacement option '-qopenmp'
Intel® Cilk™ Plus is a deprecated feature in the Intel® C++ Compiler 18.0. Prefer to use OpenMP-based syntax for offloading to the processor graphics. For more information see Migrate Your Application to use OpenMP* or Intel® Threading Building Blocks (Intel® TBB) Instead of Intel® Cilk™ Plus
icc: remark #10421: The IA-32 target wrapper binary 'icc' is deprecated. Please use the compiler startup scripts or the proper Intel(R) 64 compiler binary with the '-Qm32' option to target the intended architecture
Support for installation on IA-32 hosts has been removed. Support for generating code for 32-bit targets is supported on 64-bit hosts (only) via compiler option /Qm32
|Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804|
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