Agilex™ 5 FPGA - RTL Import Tutorial Example Design Guide Using Visual Designer Studio

This example consists of the following components:

• AXI4 Lite command/status register block implemented in RTL
• Represents a typical control/status register
• 2 AXI4 Lite command/status register blocks with command outputs connected to status inputs between each block
• On-Chip memory IP core
• JTAG Master IP core
• For System Console/Hardware Manager for lab testing of system using read/write of address mapped components
• Reset and PLL
• PLL block for system clock generation
• Reset control RTL block
• Bus Functional Module (BFM)
• Used only for simulation to create bus memory mapped transactions
• Controlled by shell_system_test.sv file that uses Verilog hierarchical referencing to control BFM
• Interconnect fabric
• Performs address decoding and AXI/Avalon inter-working