Introduction
This design demonstrates the transaction between the Nios® V processor and the PIO core for the Agilex™ 7 F-Series FPGA Development Kit.
IP Cores
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Detailed Description
The PIO core is configured for output ports only and the outputs are connected to the LED on the development kit. The application, which runs atop this design, toggles these output registers of the PIO core. The application writes and reads back the content from the IP location.
