Introduction
| IP Core | IP Core Category |
|---|---|
| Nios V Soft Processor FPGA IP - M Core | Embedded Processor |
| altera_avalon_onchip_memory2 | Other |
| altera_avalon_jtag_uart | Other |
Detailed Description
This example design includes a Nios® V/m embedded processor connected to the DMA, On Chip RAM and JTAG UART IP. The objective of the design is to accomplish a data transfer between the two On Chip RAM using a DMA (MSGDMA) IP.
DMA facilitates the data transfer which is then read back by the processor.
The UART IP then prints the application output on the terminal.
Please refer to the document for details about the design.
Prepare the design template in the Quartus Prime software GUI
Note: After downloading the design example, you must prepare the design template. The file you downloaded is of the form of a <project>.par file which contains a compressed version of your design files (similar to a .qar file) and metadata describing the project. The combination of this information is what constitutes a <project>.par file. You can simply double click on the <project>.par file and Quartus will launch that project.