Agilex™ 7 FPGA – Nios® V Processor with DMA and OCM Design Example

Agilex™ 7 FPGA – Nios® V Processor with DMA and OCM Design Example

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Introduction

This design example demonstrates a data transfer between two on-chip memory (OCM) blocks mapped to the Nios® V processor via direct memory access (DMA).

Development Kit

Intel Agilex® 7 FPGA F-Series Development Kit (Production 1 P-Tile & E-Tile) DK-DEV-AGF014EA

Design Details

Device Family	Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
Quartus Edition	Intel® Quartus® Prime Pro Edition
Quartus Version	22.4
Other Tags	Validated in Quartus and Board

IP Cores (3)

IP Core	IP Core Category
Nios V Soft Processor FPGA IP - M Core	Other
altera_avalon_onchip_memory2	Other
altera_avalon_jtag_uart	Other

Detailed Description

Development Kit

Intel Agilex® 7 FPGA F-Series Development Kit (Production 1 P-Tile & E-Tile) DK-DEV-AGF014EA

Design Details

Device Family	Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
Quartus Edition	Intel® Quartus® Prime Pro Edition
Quartus Version	22.4
Other Tags	Validated in Quartus and Board