Intel Programmable Solutions Group is Now Altera®, an Intel Company
Join us at one of our upcoming events or browse content from our past events to learn more about how we can help you overcome today’s challenges and create solutions for your business.
Upcoming Event
Altera Innovators Day: Where Developers Meet Innovation
Join us on September 23 in San Jose at Altera Innovators Day (formerly Intel FPGA Technology Day) to explore the latest advancements in FPGA technology and solutions. Engage with fellow developers, architects, and Altera experts to unlock innovation and solve complex challenges across AI, embedded, networking, and cloud applications.
Past Events
Demo Title | Description |
---|---|
Integrated Realtime ROS 2-based Robot Controller | This demonstration shows the Agilex 5 SoC capability as a ROS 2-based robot controller. The 6-axis Drive-on-Chip design, running on the FPGA fabric, controls simulated motor models that mimic the motors in the robot joints. A ROS control interface handles the interaction between the ROS framework running on the Hard Processor System (HPS) and the low-level drive control running on the FPGA fabric. A MoveIt 2-based path planning pipeline provides the necessary stream of joint information to move the robot arm. RViz running on a separate device enables visualization of the current state of the robot arm as published by the ROS control interface. |
4K Smart Cameras with Integrated MIPI D-PHY v2.5 | This demonstration shows the 4K camera processing capability of the Agilex 5 FPGA E-Series. The FPGA's built-in MIPI D-PHY v2.5 interface, CSI-2 protocol IP, modular Image Signal Processing IP, and embedded Software Stack provide a highly integrated and customizable platform for low-power, low-latency image sensor capture-and-display applications. The design architecture shows how the application can readily be extended to multi-channel systems, including specialized interfaces, AI inference and custom processing IP. |
High-Performance 8K Video & Vision Processing | This demonstration shows the high performance, low latency video processing capabilities of the Agilex 7 FPGA to ingest, process and output video at resolutions up to 8Kp60. The optimized video system, operating at 600MHz, provides a modular, flexible, and customizable design flow and utilizes the Intel Video Connectivity IP and Video and Vision Processing IP Suites. |
Improved TCO for OpenPLC Drive-on-Chip | This demonstration showcases the versatility of Agilex 5 SoC FPGA by executing containerized OpenPLC runtime on the Hard Processor System (HPS), providing a web server interface for user control from a host PC and simultaneously running a sophisticated Intel Drive-on-Chip (DoC) multi-axis design on FPGA fabric which is controlled by OpenPLC. The DoC design controls a simulated motor model running on the FPGA fabric. OpenPLC GUI running on the host PC provides the interface to control the motors. Through a JTAG interface, the DoC design connects to a separate GUI which provides motor diagnostic information. |
Easily Add Tensor Capability for non-AI Users | This TinyML demonstration highlights the AI capabilities of the next-generation Intel soft processor, Nios V. The demo showcases the implementation of a number recognition application utilizing the Tflite micro C++ library. |
Experience the power of the Intel FPGA AI Suite in action on the Agilex 5 FPGA, leveraging its AI Tensor blocks. Images stored on the SD card are seamlessly streamed to the FPGA AI Suite, emulating a real-time streaming source. | |
PCIe Gen 1-6 Data Rates on the Same Transceiver | Agilex 7 FPGAs with F-Tile FGT transceivers, capable of supporting data rates of up to 32Gbps NRZ and up to 58Gbps PAM4, and has also been shown to achieve 64Gbps PAM4 data rate for PCIe 6.0 data rates and encodings. The Agilex 7 F-tile FGT is the only transceiver available in an FPGA capable of supporting PCIe Gen1-6 data rates in the same transceiver. This design example demonstrates Agilex 7 F-Tile transceivers transmitting and receiving PRBS data at all PCIe 6.0 rates. |
Marine Radar and Scalable DSP Performance | This demonstration shows the advanced Digital Signal Processing (DSP) capabilities of the Agilex 5 FPGA E-Series within the context of a marine radar application. DSP techniques such as Pulse Compression and Doppler FFT are efficiently implemented through a Simulink-based design flow to determine the range and radius to objects of interest. |
Depth Map Processing for Intel® RealSense™ Cameras | This demonstration shows how the Agilex SoC FPGA can seamlessly integrate with an Intel RealSense camera via the Hard Processor System (HPS) controlled USB port to stream pixel and depth data to the HPS DDR memory. Simultaneously, an FPGA video pipeline made of Intel Video Processing IP Suite and Intel Video Connectivity IPs reads the frame data from DDR to create a 2D heat map view and outputs to the display. |
Time | Location | Duration | Speaker | Session Title | Abstract/Description |
---|---|---|---|---|---|
10:30 – 11:00 |
Booth |
30 min |
Giuseppe Privitera |
Introduction to Agilex™ 5 FPGAs7 |
This module discusses how Agilex 5 FPGAs solve design challenges through adaptability, power-efficient performance, and best-in-class developer tools to increase productivity. |
11:30 – 12:00 |
Conference Center |
30 min |
Alexey Lopich |
Designing Genlocked Video Systems with Deterministic Low Latency on FPGAs |
|
12:30 – 13:00 |
Exhibitor Forum |
30 min |
Adam Titley |
Consolidated Robot Controller on Altera SoC FPGA devices |
In this short presentation, we will discuss the needs of a consolidated robotics controller and how Altera SoC FPGA devices can be used in this demanding application space. |
13:30 – 14:30 |
Exhibitor Forum |
30 min |
Deepali Trehan |
Panel: C-level @ EW |
For the first time, Embedded World organized a high-level panel with leading personalities from the industry. The aim is to discuss general trends, overarching challenges and looming opportunities, and thus to increase the range of the event. Other panelists include Infineon and Qualcomm. |
15:30 – 16:00 |
Booth |
30 min |
Stefan Garcia |
Agilex™ 5 FPGA Hardened Processor Subsystem (HPS) | This seminar discusses the capabilities of this HPS, highlighting the differentiating technical features and innovations. These uplifts and upgrades deliver higher performance and lower total power consumption compared to prior-generation FPGA SoCs. |
Time | Location | Duration | Speaker | Session Title | Abstract/Description |
---|---|---|---|---|---|
10:30 – 11:00 |
Booth |
30 min |
Jean Michel Vuillamy |
DSP with AI Tensor Block |
This module discusses the upgraded features, why they were implemented, and how they will help solve next-generation compute challenges at the edge of the network for a wide variety of applications. |
11:00 – 11:30 |
Conference Center |
30 min |
Alexey Lopich |
High-Performance Image Signal Processing and Camera Sensor Pipeline Design on FPGAs |
|
11:30 – 12:00 |
Conference Center |
30 min |
Alex Huntley |
SoC-FPGA Architecture for Functional Safety according to ISO 13849-1 Cat. 3 PL d SIL2 |
|
12:30 – 13:00 |
Exhibitor Forum |
30 min |
Angelo Lo Cicero |
Security and Safety with Altera FPGAs |
In this short presentation, we will highlight using FPGAs to solve safety and security challenges. |
13:30 – 14:00 |
Booth |
30 min |
Peter Brookes |
Agilex 5 FPGAs for Video Solution |
This module covers video solutions such as a camera pipeline supporting 4K resolution MIPI CSI-2 input, 4K & 8K UDX (Up-Down Cross Conversion) design, 4K Warp, TMO, 3D LUT (WT3) pipeline with low latency, and more. |
15:30 – 16:00 |
Booth |
30 min |
Esteban Valverde |
Network IP - Ethernet & Time-Sensitive Networking (TSN) |
This module We’ll discuss Ethernet modes supported and identify use cases targeted for the Agilex 5 market. We will also discuss TSN (Time-Sensitive Networking) support and the growing markets that will be addressed. |
Time | Location | Duration | Speaker | Session Title | Abstract/Description |
---|---|---|---|---|---|
10:30 – 11:00 |
Booth |
30 min |
Stefan Garcia |
Implementing Nios® V Processors |
This module discusses the benefits of Nios V processors for Agilex 5 devices, software and hardware development tools and options from the RISC-V ecosystem available to develop your target applications. |
12:30 – 13:00 |
Exhibitor Forum |
30 min |
Jean Michel Vuillamy |
AI: A One-Size-Fits-All Approach Isn't Practical |
This presentation will describe the Intel FPGA AI suite and how it can be used to enhance your product with this exciting capability. |
Our Vision as a Standalone Business
Intel FPGA Technology Day (IFTD) 2023
Browse our disclosures and launches at IFTD 2023
Intel Agilex® 3 FPGAs B-Series and C-Series Revealed
The power and cost-optimized members of the Intel Agilex® FPGA portfolio have been revealed, with B-Series targeted at board and system management applications, and C-Series targeted for a breadth of CPLD & FPGA applications.
Intel Agilex® 5 FPGAs E-Series Expands Early Access Program
Intel Agilex 5 FPGAs E-Series designed for the embedded edge, will begin engineering sample shipments to early access customers in Q4 2023. Intel® Simics® Simulator for Intel FPGAs, a complete system simulator for software development, will be available in Q1 2024 for the E-series devices.
Intel Agilex® 7 FPGAs Shipping CXL IP with 2.0 Features in Volume
Intel Agilex® 7 FPGAs with R-Tile, capable of PCIe 5.0 x16 and CXL 1.1/2.0, are now shipping in volume, enabling customers to ramp into production today with standard lead times.
Nios® V/c Compact Microcontroller Launched
Nios V/c Compact joins an already robust family of Nios V soft-core processors, enabling open-source RISC-V architecture-based functionality on Intel FPGAs.
First F2000X IPU Production Adapters Launched
Napatech’s F2070X IPU adapters are in production and available now, enabling TCO improvements for cloud and networking applications.
Open FPGA Stack (OFS) Open Source Launched
Developers now have full access to the open source Open FPGA Stack (OFS) hardware code, software code, and technical documentation for platform and workload development.