Intel Researchers Usher In '3-D' Era In Transistor Design

Three-Dimensional 'Tri-Gate' Transistors an Alternative to Traditional Flat Planar Transistors

TOKYO, JAPAN, Sept. 19, 2002 -- Intel researchers have developed a three-dimensional (3-D) "tri-gate" transistor design that achieves higher performance with greater power efficiency than traditional planar (flat) transistors. This development provides the first glimpse of a new era of non-planar 3-D transistor designs that Intel and the semiconductor industry must implement to maintain the pace of Moore's Law beyond this decade.

"Our research shows that below 30 nanometers, the basic physics of the flat, single-gate planar transistor leaks too much power to meet our future performance goals," said Dr. Gerald Marcyk, director of the Components Research Lab at Intel. "The tri-gate transistor design will allow Intel to build ultra-small transistors that achieve high performance with low power and continue driving the pace of Moore's Law."

A New 3-D Transistor Era
Transistors are the microscopic, silicon-based switches that process the ones and zeros of the digital world and are the fundamental building block of all semiconductor chips. With traditional planar transistors, electronic signals travel as if on a flat, one-way road. This approach has served the semiconductor industry well since the 1960s. But, as transistors shrink to less than 30 nanometers (billionths of a meter), the increase in current leakage means that transistors require increasingly more power to function correctly, which generates unacceptable levels of heat.

Intel's tri-gate transistor employs a novel 3-D structure, like a raised, flat plateau with vertical sides, which allows electronic signals to be sent along the top of the transistor and along both vertical sidewalls as well. This effectively triples the area available for electrical signals to travel, like turning a one-lane road into a three-lane highway, but without taking up more space. Besides operating more efficiently at nanometer-sized geometries, the tri-gate transistor runs faster, delivering 20 percent more drive current than a planar design of comparable gate size.

The tri-gate structure is a promising approach for extending the TeraHertz transistor architecture Intel announced in December 2001. The tri-gate is built on an ultra-thin layer of fully depleted silicon for reduced current leakage. This allows the transistor to turn on and off faster, while dramatically reducing power consumption. It also incorporates a raised source and drain structure for low resistance, which allows the transistor to be driven with less power. The design is also compatible with the future introduction of a high K gate dielectric for even lower leakage.

Intel researchers will discuss major elements of the new tri-gate transistors at the International Solid State Device and Materials Conference in Nagoya, Japan, on Sept. 17. Intel's technical paper will address performance, power consumption and current leakage with significant improvements to existing transistor design.

For more information on the 3-D tri-gate transistor and other silicon research at Intel, visit Intel's Silicon Showcase at www.intel.com/research/silicon.

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