Intel Completes 0.13 Micron Process Technology Development

HILLSBORO, Ore., Nov. 7, 2000 - Intel Corporation today announced that it had completed the development of its 0.13 micron (130 nanometer) generation logic technology, allowing it to manufacture chips with transistors that are approximately 1/1000th the width of a human hair. An important milestone in Intel's continuing quest to make computer chips smaller and more powerful, this advanced process technology will begin volume manufacturing next year and deliver a new generation of high performance microprocessors, which may contain more than 100 million transistors and run at multi-GHz clock speeds.

The company has built functional static RAMs and microprocessors using this technology, which features 70 nm transistor gate width, 1.5 nm gate oxide thickness, copper interconnects, and low-k dielectrics. (A nanometer is one billionth of a meter.) Intel is the first to complete development of the 130 nm generation process technology and to demonstrate its manufacturing readiness with complex integrated circuits. Intel will present details of this process technology at the International Electron Devices Meeting (IEDM) in December 2000.

"This accomplishment reaffirms our faith in Moore's Law," said Sunlin Chou, Intel vice president and general manager of the Technology and Manufacturing Group. "It is a credit to our development teams who have repeatedly overcome rising technical challenges to accelerate the arrival of new generations of silicon technology." Today's announcement extends Intel's 10-year track record of introducing a new process technology every two years.

"Intel's 130nm process incorporates an unusually large number of simultaneous technology advancements," added Chou. "We started working on these advancements several years ago. We believe that our 130nm process will be the earliest to ramp into volume production and to deliver products with leading edge performance, density, and power efficiency."

World's Fastest Transistors and High Performance Interconnects
Intel's 130 nm process technology features the world's fastest transistor -- the foundation of fast microprocessors. To achieve this, Intel uses a small transistor gate and the thinnest of thin films to make these ultra fast transistors. Intel's transistor gate measures just 70 nm (0.07 microns in length), the smallest in the industry. The technology also features a 1.5 nm gate oxide that is the thinnest in the industry for a manufacturing technology. The 1.5 nm gate oxide provides industry leading transistor performance at lower operating voltage.

Besides the ultra-small transistor gate and thin oxides, Intel's 130 nm logic technology has high performance interconnect technology featuring six-layers of dual damascene copper. Copper is a better conductor of electrical current than aluminum, which was the metallization material used in earlier Intel process technology generations. Intel maintains a high-aspect-ratio (thickness/width) of 1.6:1 with its metal lines, so while decreasing line width to provide better density, metal is kept thick to reduce line resistance.

Wire capacitance is kept low with low-k dielectric of fluorine-doped SiO2 insulator (dielectric constant of 3.6). Low-k dielectric is the insulation between the layers of metallization. Good insulation isolates electric signals keeping the signals from contaminating each other.

The combination of faster transistors and high-performance interconnects of Intel's 130 nm process will enable the speed of microprocessor circuits of up to 65 percent relative to that attained with 180 nm technology.

Lower Power and Cost
Intel's 130 nm logic process will operate at 1.3 volts or less, lowering the voltage over today's state-of-the-art technologies by 20 percent. This will reduce power consumption and increase battery life in microprocessors targeted for mobile computing.

As cache memory sizes in microprocessors increase, the SRAM cell size has greater effect on the chip area and manufacturing cost. Intel has focused on reducing SRAM cell size in its 130 nm process. High-yielding 18-Mbit SRAM chips have been made with a six-transistor SRAM cell size of 2.45 square-microns, which is 2.3X smaller than that of the 180 nm process. An even smaller 2.09 square-micron SRAM cell is under development and will make these SRAM cells the smallest yet reported in the industry.

As previously announced, Intel plans to begin production of its 130 nm process on 300 mm wafers in 2002, about a year after production begins on 200 mm wafers. Chip fabrication cost on 300 mm wafers will be at least 30 percent lower than that on 200 mm wafers.

Manufacturing Readiness Demonstrated
Intel continues its practice of using product-like test vehicles to demonstrate and refine new process capabilities. Wafers containing an 18-Megabit SRAM test vehicle have been fabricated on the 130 nm process over the past year. This SRAM test vehicle currently operates at greater than 1.6 GHz, with higher speeds expected as the process is further enhanced. Microprocessors have also been fabricated, and operate faster than on 180 nm technology.

For more information on Intel silicon technology, please reference Intel's new Silicon Showcase at www.intel.com/research/silicon.

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