Intel Activates Its 300 Millimeter Wafer Program

30 Percent Cost Reduction Expected with Transition to Larger Wafer Size

SANTA CLARA, Calif., June 9, 1999 -- Intel Corporation is activating its 300 millimeter (mm) wafer development program, the company announced today. The larger wafer size represents more than a doubling of the silicon wafer's surface versus today's standard 200 mm wafer. The use of 300 mm wafers is expected to cut high-volume chip fabrication cost by 30 percent when compared to 200 mm wafer production costs.

Intel plans to start 300 mm production on a 0.13 micron process with copper metallization in 2002, about one year after it begins 0.13 micron production on 200 mm wafers. The 300 mm process technology development will be carried out at Intel's D1C development fab in Oregon, where equipment installation is scheduled to begin in early 2000.

"The road to the Internet is paved with silicon. With a billion computers connected to the Internet, a huge volume of silicon building blocks will be required. The 300 mm wafers will help us get there more cost effectively and Intel believes it is the time for the industry to move to a new, larger wafer generation," said Dr. Craig Barrett, Intel president and chief executive officer.

Improved Productivity, Lower Costs
The 300 mm (12-inch) wafer offers 225 percent of the silicon surface area (over twice as much surface area), and about 240 percent of the printed die (individual computer chips) per wafer, relative to standard 200 mm (8-inch) wafers used in many semiconductor manufacturing plants today.

"We can improve our productivity and this will result in lowering our costs by approximately 30 percent for each chip produced on the larger wafer," noted Michael Splinter, Intel senior vice president and general manager of the Technology and Manufacturing Group. "We have been working with numerous industry consortia as well as silicon and equipment suppliers to determine the industry's readiness. Intel believes the technology and capabilities are now poised to bring 300 mm wafers into high volume manufacturing."

While lowering costs, Intel expects to reach levels of performance and reliability on larger wafers that are equivalent to what was attained with 200 mm wafers.

"Larger wafers give the industry the opportunity to improve productivity, allowing Intel to bring ever-more-powerful semiconductor chips at lower costs to consumers around the world," added Splinter.

0.13 Micron Process Technology
Intel has started ramping its industry-leading 0.18 micron process technology into high volume manufacturing. By next year, Intel expects to be making almost all of its microprocessors on this advanced technology in five different fabrication plants around the world.

"With our 0.18 micron process technology now in production, it is time to aggressively step up our pursuit of our next generation process technology development," explained Sunlin Chou, Intel vice president and general manager of the Technology and Manufacturing Group. "We plan to be the first to ramp production on 0.13 micron technology with copper metallization, initially on 200 mm wafers, and then on 300 mm wafers."

D1C Technology Development Fab
Intel's D1C Development Fab will be located in Hillsboro, Oregon. The facility will include a clean room, which is approximately 120,000 square feet. D1C is projected to cost about $1.2 billion over the next several years to build and equip during its development phase.

Since the fab will be developing 0.13 micron process technology for 300 mm wafers, the new manufacturing equipment will be specifically designed for this new wafer generation. Intel uses equipment from the top suppliers around the world.

The new process technology will produce advanced microprocessors and other semiconductor products that will be the future versions of the company's Pentium® III, Pentium III Xeon™, and Intel® Celeron® processors. In addition, Intel's new IA-64 microprocessors will take advantage of this future manufacturing technology.

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