Intel Corporation Announces New Low Pin Count (LPC) Interface Specification To Facilitate Industry Legacy Migration Toward Future ISA-Less Systems

Intel's LPC Specification Helps PC Desktop and Mobile OEMs and IHVs Lower Overall Development Costs through Streamlined Legacy I/O Design

INTEL DEVELOPER FORUM, SAN FRANCISCO, Sept. 29, 1997-- Intel Corporation announced today at its Intel Developer Forum a new Low Pin Count (LPC) Interface Specification for legacy I/O, which will further drive the industry's transition from ISA bus-based systems to PCI bus-based platforms. Intended for both notebook and desktop PC OEMs and IHVs, the newly defined LPC Interface allows the legacy I/O motherboard components, typically integrated in a Super I/O chip, to migrate from the ISA/X-bus to the LPC Interface, while retaining full software compatibility. This will allow manufacturers to reduce overall design costs and facilitate the industry's move toward higher performance next-generation I/O technologies, such as Universal Serial Bus (USB) and IEEE1394.

The new specification allows for a three-phase legacy migration. First, on-board ISA/X-bus legacy I/O peripherals, such as floppy disk controller, parallel port and keyboard controller, will move to the LPC Interface, while non-legacy functions, such as modems, are transitioning to USB. The next phase will be the removal of ISA slots, thereby migrating expansion to higher bandwidth PCI slots inside the box with additional expansion available via USB and 1394 outside the box. ISA slots may become optional during this phase of the transition. The final phase removes legacy serial and parallel ports as native USB and 1394 peripherals become ubiquitous.

The LPC Interface Specification Revision 1.0, and an associated reciprocal, royalty-free patent license, are available from the Intel Web site.

"As the industry moves toward more powerful, higher bandwidth solutions, it becomes a burden to carry the older, legacy technologies because of the higher pin counts which require more space, cost and testing procedures," said Jan Camps, marketing manager for Intel's Platform Component Division. "Through our R&D efforts, we have found a way to facilitate this migration, which will result in lower costs and improved efficiency for hardware OEMs and developers, and make the benefits of higher performing technologies available more quickly for PC users. Intel has opened the specification so the industry can quickly adopt the technology and integrate it into motherboard legacy I/O peripheral development."

The new LPC Interface Specification calls for a new interface between the core logic chipset and motherboard legacy I/O functions and offers several key advantages. It is a component interface replacing X-Bus/ISA over time, which reduces pin counts for easier, more cost-effective design. The LPC Interface Specification is software transparent for I/O functions and compatible with existing peripheral devices and applications.

The LPC Interface Specification describes memory, I/O and DMA transactions. Unlike ISA, which runs at 8 MHz, it will use the PCI 33 MHz clock and will be compatible with more advanced silicon processes. Mobile designers will also benefit from the reduced pin count because it uses less space and power, and is more thermal efficient.

Several peripheral manufacturers are already planning to adopt the LPC Interface Specification in their future peripheral designs.

"In support of the new LPC Interface Specification, we have developed a Super I/O device which takes advantage of the design cost savings," said Michael Maia, director of the Americas Division Personal Systems Group for National Semiconductor. "The entire industry will benefit from the technology combination of National's I/O leadership and Intel's architectural expertise in this area."

"We already have the LPC specification integrated into our plans," said Robert Hollingsworth, vice president, marketing from Standard Microsystems Corporation. "This type of leadership helps the industry, as a whole, migrate to more cost-effective solutions."

OEMs and developers can receive further information on LPC or download the new interface specification by visiting the Intel web site at Intel™ Chip Set Web Site. The semiannual Intel Developer Forum is a three-day intensive forum providing hardware OEMs and IHVs in-depth information on Intel technologies and initiatives. More information on the Intel Developer Forum can be found on the Intel web site www.intel.com/idf.

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