PCI* Express Reference Designs and Application Notes
Intel® FPGA offers a host of PCI Express (PCIe*) reference designs and application notes. These reference designs and application notes offer
ready-made solutions that can leveraged for feasibility studies, device selections, and design proofing on Intel FPGAs and SoCs.
The Intel FPGA development kits complement the reference designs and application notes by delivering a complete system-level design environment that includes both the hardware and software needed to immediately begin developing designs. Each reference design indicates which Intel FPGA development kit and version of the Quartus® II software were used for its development cycle.
As PCIe is a very configurable intellectual property (IP) solution and supports numerous application needs, we cannot offer reference designs for every configuration or application possible. If there is no readily available reference design for your particular configuration or device, you may use a similar design and modify and/or port it as needed to fit your design requirements.
Table 1 describes the various reference designs and application notes available for PCIe applications.
Table 1. Reference Design and Application Note Support
Name |
Application Note/ |
Development Kit Used |
Quartus II Software Version |
Design Flow Qsys/MW2/ |
EP/RP1 |
AVST3/ |
User Interface/ |
---|---|---|---|---|---|---|---|
PCIe with External Memory Interface Reference Design |
|||||||
PCIe AVMM with Direct Memory Access (DMA) and DDR3 Memory Interface |
Stratix® V GX FPGA Development Kit |
14.0 |
Qsys |
EP |
AVMM with DMA |
256 bit: Gen3x8 |
|
PCIe with On-chip Memory Interface Reference Designs |
|||||||
PCIe AVMM with DMA and On-Chip Memory Interface |
AN690 |
Stratix V GX FPGA Development Kit |
14.0 |
Qsys |
EP |
AVMM with DMA |
256 bit: Gen3x8 |
Arria® V GT FPGA Development Kit Arria V GX Starter Kit |
Pre-14.0 release5 |
Qsys |
EP |
AVMM with DMA |
128 bit: Gen2x4 Linux |
||
Cyclone® V GT FPGA Development Kit |
|||||||
PCIe AVMM with DMA and On-Chip Memory Interface (Linux Driver) |
|
||||||
PCIe with Single-root I/o Virtualization (Sr-iov) Reference Design |
|||||||
Stratix V GX FPGA Development Kit |
14.0 |
Qsys |
EP |
AMM with DMA |
256 bit: Gen3x8 |
||
PCIe with On-chip Memory Interface Reference Designs |
|||||||
Stratix V GX FPGA Development Kit |
14.0 |
Qsys |
EP |
Avalon-ST |
64 bit: Gen1x1, |
||
Arria V GT FPGA Development Kit |
64 bit: Gen1x1, |
||||||
Cyclone V GT FPGA Development Kit |
64 bit: Gen1x1, |
||||||
Stratix IV GX FPGA Development Kit |
64 bit: Gen1x1, |
||||||
Cyclone IV GX FPGA Development Kit |
Hardened Protocol Stack IP Use |
||||||
Arria II GX FPGA Development Kit |
Hardened Protocol Stack IP Use |
||||||
PCIe with External Memory Interface Reference Designs (Legacy Reference Designs) |
|||||||
PCIe AVST / AVMM and DDR2 / DDR3 Memory Interface |
AN431 |
Stratix IV GX FPGA Development Kit Arria II GX FPGA Development Kit |
11.0 SP1 |
Qsys |
EP |
AVST / AVMM |
64 bit: Gen2x4 Hardened Protocol Stack IP Use |
Other PCIe Collateral Items and Tools |
|||||||
MSI-X Implementation Guidelines for Intel FPGAs |
All |
14.0 |
N/A |
EP |
AVST / AVMM |
N/A |
|
Transceiver Toolkit for hardened PCIe IP (Gen1x8) |
FPGA Wiki | Stratix V GX FPGA Development Kit | 13.1 | Qsys | EP | AVST | 128 bit: Gen1x8, Gen2x8 256 bit: Gen3x8 |
Notes to Table
- EP = Endpoint, RP = Root Port
- MW = MegaWizard
- AVST = Avalon® Streaming (Avalon-ST)
- AVMM = Avalon Memory-Mapped (Avalon-MM)
- Actual project is generated and compiled in Quartus II software v14.0 (internally released build) and is moved to Quartus II software v13.1 (public release). This enables customers to use designs while Intel FPGA completes the formal documentation release process of the upcoming Quartus II software publically released version.
Figure 1. Typical PCIe Application
