External Memory - SRAM
SRAM
QDR II/QDR II+ / QDR II+Xtreme / QDR IV SRAM devices enable you to maximize memory bandwidth with separate read and write ports. The QDR SRAM architecture features two data ports operating twice per clock cycle to deliver a total of four data words per cycle. The resulting performance increase is particularly valuable in bandwidth-intensive applications.
Intel offers a complete PHY and controller solution for building a QDR II/QDR II+/QDR II+Xtreme/QDR IV SRAM interface in Intel® FPGAs. The External Memory Interface Support Center shows the QDR II/QDR II+/QDR II+Xtreme/QDR IV SRAM memory interface performance of Intel FPGAs.
Technical Documentation
Intel offers the following technical documentation that contains information on device support for the QDR and QDR II memory interfaces, as shown in Table 1.
Table 1. QDR II SRAM Technical Documentation
Software Support and Tools
Intel offers the tools shown in Table 3 to aid in the QDR II and QDR II+ SRAM memory interface design process.
Table 3. QDR II SRAM Software and Support Tools
Feature |
Applicable Devices |
---|---|
All |
|
All |
IP Cores and Reference Designs
Table 4 lists QDR II SRAM controller intellectual property (IP) cores and reference designs available from Intel.
Table 4. QDR II SRAM IP Cores and Reference Designs
Controller Name |
Free Evaluation |
Vendor |
Devices Supported |
---|---|---|---|
QDR II SRAM Controller MegaCore Function | Yes | Intel | Stratix V, Stratix IV, Stratix III, Stratix II, Stratix II GX, Stratix, Stratix GX |
Development Kits and Hardware Reference Platforms
Table 5 lists memory hardware reference platforms available from Intel. The Gerber files, layout, termination recommendations, and signal integrity analysis information of these reference platforms are also available.
Table 5. QDR II SRAM Development Kits and Hardware Reference Platforms
Board Name |
Vendor |
Contact Information |
---|---|---|
QDR II SRAM Stratix Memory Reference Platform | Intel | Contact your local Intel FAE |