NAND Flash Devices
The main advantage of the NAND flash devices is large storage capacity.
The disadvantages of NAND flash devices include:
- A high pin count requirement (a minimum of 15 pins are required)
- More difficult to manage, as individual bit reliability is lower compared to quad SPI flash, error correction, and bad block management are required
- Lower maximum bandwidth as compared to quad SPI flash devices
The NAND flash devices are typically used for mass data storage, but they can also be used as a boot source.
The NAND flash devices to be used with Intel Arria 10 SoC must satisfy at least the following requirements:
- ONFI 1.0 compatibility
- x8 interface for boot devices, x16 supported for general data storage
- Single-level cell (SLC) or multi-level cell (MLC)
- Only one ce# and rb# pin pair is available for the boot source. Up to three additional pairs are available for mass storage.
- Page size: 512 bytes, 2 KB, 4 KB or 8 KB
- Pages per block: 32, 64, 128, 256, 384, or 512
- Error correction code (ECC) sector size can be programmed to 512 bytes (for 4, 8, or 16 bit correction) or 1,024 bytes (for 24 bit correction)
The current list of tested and supported devices is presented below: