Intel® FPGA Package and Thermal Information

Package information includes the ordering code reference, package acronym, leadframe material, lead finish (plating), JEDEC® outline reference, lead coplanarity, weight, moisture sensitivity level, and other special information. The thermal resistance information includes device pin count, package name, and resistance values.

Intel Agilex® 7 Family

Intel® Stratix® Series

Intel® Arria® Series

Intel® Cyclone® Series

Intel® MAX® Series

Serial Configuration Devices

Package Mechanical Drawings

Intel® Stratix® 10 devices

Intel® Arria® 10 devices

Intel® Cyclone® 10 devices

Intel® MAX® 10 devices

EPCQ-A

Package Ball Coordinate Lists

Stratix® V devices

Arria® V devices

Cyclone® V devices

MAX® V devices

EPCQ-L

Manufacturing Advantage Services (MAS)1

Stratix® IV devices

Arria® II devices

Cyclone® IV devices

MAX® II devices

EPCQ

Compact Thermal Models1

Stratix® III devices

 

Cyclone® III devices

 

EPCS
      Cyclone® II devices    
For other devices not listed in Table 1, please see the Package Information Datasheet for Mature devices, or visit the Intel® FPGA device and support collection to find more information about Mature and Legacy Device Support Collections.
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Note 1 – Compact Thermal Models and MAS documents for Intel Agilex® 7 Devices are restricted access, please sign in or register to access.

For PCB Manufacturing Information and Resources visit the Board Developer Center.