Literature: MAX® Devices
MAX® V Device Handbook (4 MB)
Section I. MAX V Device Core
- Chapter 1. MAX V device family overview (ver 1.2, May 2011, 186 KB)
- Chapter 2. MAX V device architecture (ver 1.0, Dec 2010, 604 KB)
- Chapter 3. DC and switching characteristics for MAX V devices (ver 1.2, May 2011, 477 KB)
- AN 629: Understanding timing in Intel® FPGA CPLDs
Section II. System Integration in MAX V Devices
- Chapter 4. Hot socketing and power-on reset in MAX V devices (ver 1.0, Dec 2010, 320 KB)
- Chapter 5. Using MAX V devices in multi-voltage systems (ver 1.0, Dec 2010, 298 KB)
- Chapter 6. JTAG and in-system programmability in MAX V devices (ver 1.1, May 2011, 217 KB)
- AN 100: In-system programmability guidelines
- AN 425: Using the command-line jam STAPL solution for device programming
- AN 628: Using the agilent 3070 tester for in-system programming in Intel FPGA CPLDs
- AN 630: Real-time ISP and ISP clamp for Intel FPGA CPLDs
- Chapter 7. User flash memory in MAX V devices (ver 1.1, Jan 2011, 1 MB)
- AN 631: Replacing serial EEPROMS with user flash memory in Intel FPGA CPLDs
- Chapter 8. JTAG boundary-scan testing for MAX V devices (ver 1.0, Dec 2010, 656 KB)
Related Documentation
Power and Thermal Management
- MAX V PowerPlay early power estimator (ver 12.0, May 2011, 7 KB)
(Final)
PowerPlay early power estimator for Intel FPGA CPLDs user guide (1 MB)
DSP
- Intel FPGA's 28 nm device portfolio (ver 3.0, Apr 2014, 1 MB)
Design Guidelines
- AN 114: Designing with high-density BGA packages for Intel FPGA devices (ver 5.3, Sep 2014, 844 KB) UPDATED
Development Kits
- MAX V CPLD development board reference manual (ver 1.0, Jan 2011, 1,009 KB)
- MAX V CPLD development kit (ver 1.0, Dec 2010, 631 KB)
- MAX V CPLD development kit user guide (ver 1.0, Jan 2011, 3 MB)
End Applications
- AN 100: In-system programmability guidelines (ver 2014.09.22, Sep 2014, 534 KB) UPDATED
- AN 485: Serial peripheral interface host in Intel FPGA MAX series (ver 2014.09.22, Sep 2014, 474 KB) UPDATED
Design example for MAX® II (305 KB)
- AN 486: SPI to I2C using Intel FPGA MAX series (ver 2014.09.22, Sep 2014, 468 KB) Updated
Design example for MAX II (385 KB)
- AN 488: Stepper motor controller using Intel FPGA MAX series (ver 2014.09.22, Sep 2014, 454 KB) UPDATED
Design example for MAX II (350 KB)
- AN 490: Intel FPGA MAX series as voltage level shifters (ver 2014.09.22, Sep 2014, 511 KB) UPDATED
Design example for MAX II (147 KB)
- AN 491: Auto start using Intel FPGA MAX series (ver 2014.09.22, Sep 2014, 473 KB) UPDATED
Design example for MAX II (245 KB)
- AN 492: CF+ interface using Intel FPGA MAX series (ver 2014.09.22, Sep 2014, 512 KB) UPDATED
Design example for MAX II (346 KB)
- AN 493: I2C battery gauge interface using Intel FPGA MAX series (ver 2014.09.22, Sep 2014, 504 KB) UPDATED
Design example for MAX II (465 KB)
- AN 494: GPIO pin expansion using I2C bus interface in Intel FPGA MAX series (ver 2014.09.22, Sep 2014, 475 KB) UPDATED
Design example for MAX II (273 KB)
- AN 500: NAND flash memory interface with Intel FPGA MAX series (ver 2014.09.22, Sep 2014, 482 KB) UPDATED
Design example for MAX II (187 KB)
- AN 501: Pulse width modulation using Intel FPGA MAX series (ver 2014.09.22, Sep 2014, 506 KB) UPDATED
Design example for MAX II (279 KB)
- AN 502: Implementing SMBus controller in Intel FPGA MAX series (ver 2014.09.22, Sep 2014, 482 KB) UPDATED
Design example for MAX II (2 MB)
- AN 509: Multiplexing SDIO devices using Intel FPGA MAX series (ver 2014.09.22, Sep 2014, 474 KB) UPDATED
Design example for MAX II (721 KB)
- Intel FPGA's 28 nm device portfolio (ver 3.0, Apr 2014, 1 MB)
- AN 265: Using Intel FPGA MAX series as microcontroller I/O expanders (ver 2014.09.22, Sep 2014, 658 KB) UPDATED
Design example for MAX II, MAX V, and MAX® 3000A (8 KB)
- AN 286: Implementing LED drivers in Intel FPGA MAX series (ver 2014.09.22, Sep 2014, 578 KB) UPDATED
Design example for MAX II (3 KB)
- AN 294: Crosspoint switch matrices in Intel FPGA MAX series (ver 2014.09.22, Sep 2014, 584 KB) UPDATED
Design example for MAX II and MAX 3000A: 16 x 16 crosspoint switch (6 KB)
Design example for MAX II and MAX 3000A: Customized crosspoint switch (7 KB)
- AN 425: Using the command-line jam STAPL solution for device programming (ver 2014.09.22, Sep 2014, 1 MB) UPDATED
- AN 495: IDE/ATA controller using Intel FPGA MAX series (ver 2014.09.22, Sep 2014, 654 KB) UPDATED
Design example for MAX II (418 KB)
- AN 496: Using the internal oscillator in Intel FPGA MAX series (ver 2014.09.22, Sep 2014, 504 KB) UPDATED
Design example for MAX II (230 KB)
Design example for MAX V (257 KB)
- AN 498: LED blink using power sequencing in Intel FPGA MAX series (ver 2014.09.22, Sep 2014, 453 KB) UPDATED
Design example for MAX II (168 KB)
- AN 630: Real-time ISP and ISP clamp for Intel FPGA MAX series (ver 2014.09.22, Sep 2014, 529 KB) UPDATED
- AN 631: Replacing serial EEPROMs with user flash memory in Intel FPGA MAX series (ver 2014.09.22, Sep 2014, 427 KB) UPDATED
- Implementing the top five control-path applications with low-cost, low-power CPLDs (ver 1.1, Jan 2011, 521 KB)
- MAX V CPLDs (ver 1.0, Dec 2010, 144 KB)
General Device Documentation
- AN 628: Using the agilent 3070 tester for in-system programming in Intel FPGA CPLDs (ver 1.0, Dec 2010, 365 KB)
- AN 629: Understanding timing in Intel FPGA CPLDs (ver 1.0, Dec 2010, 406 KB)