Literature: HardCopy® III Devices

Literature: HardCopy III Devices

HardCopy III Device Handbook, Volumes 1, 2, and 3 (6 MB)

HardCopy III Device Handbook, Volume 1: Device Interfaces and Integration (ver 3.4, Mar 2012, 3 MB)

Section I. Device Core

• Chapter 1. HardCopy III device family overview (ver 3.2, Jan 2011, 297 KB)
• Chapter 2. Logic array block and adaptive logic module implementation in HardCopy III devices (ver 2.1, Jan 2011, 140 KB)
• Chapter 3. DSP block implementation in HardCopy III devices (ver 2.1, Jan 2011, 165 KB)
• Chapter 4. TriMatrix embedded memory blocks in HardCopy III devices (ver 3.1, Jan 2011, 147 KB)
• Chapter 5. Clock networks and PLLs in HardCopy III devices (ver 3.1, Jan 2011, 203 KB)

Section II. I/O Interfaces

• Chapter 6. I/O Features for HardCopy III device (ver 3.1, Jan 2011, 331 KB)
• Chapter 7. External Memory interfaces in HardCopy III devices (ver 3.2, Mar 2012, 785 KB)
• Chapter 8. High-Speed differential I/O interfaces and DPA in HardCopy III devices (ver 3.2, Jan 2011, 737 KB)

Section III. Hot Socketing and Testing

• Chapter 9. Hot socketing and power-on reset in HardCopy III devices (ver 2.1, Jan 2011, 262 KB)
• Chapter 10. IEEE 1149.1 (JTAG) boundary scan testing in HardCopy III devices (ver 3.1, Jan 2011, 147 KB)

Section IV. Power and Thermal Management

• Chapter 11. Power management in HardCopy III devices (ver 3.2, Jan 2011, 226 KB)

Section V. Packaging Information

• Chapter 12. HardCopy III device and packaging information (ver 3.1, Jan 2011, 114 KB)

HardCopy III Device Handbook, Volume 2: Design Flow and Prototyping (ver 3.3, Mar 2012, 2 MB)

Section I. HardCopy III Design Flow and Prototyping with Stratix® III Devices

• Chapter 1. HardCopy III design flow using the Quartus® II software (ver 3.3, Mar 2012, 882 KB)
• Chapter 2. HardCopy design center implementation process (ver 2.1, Jan 2011, 219 KB)
• Chapter 3. Mapping Stratix III device resources to HardCopy III devices (ver 3.3, Mar 2012, 271 KB)
• Chapter 4. Matching Stratix III power and configuration requirements with HardCopy III devices (ver 3.2, Mar 2012, 504 KB)

HardCopy III Device Handbook, Volume 3: Datasheet and Addendum (ver 3.3, Mar 2012, 872 KB)

Section I. HardCopy III Device Datasheet

• Chapter 1. DC and switching characteristics of HardCopy III devices (ver 4.1, Dec 2011, 364 KB)
• Chapter 2. Addendum: Extended temperature range for HardCopy III devices (ver 1.0, Mar 2012, 136 KB)

Related Documentation

External Memory Interfaces

• AN 550: Using the DLL phase offset feature in Stratix FPGAs and HardCopy ASICs (ver 2.0, Mar 2010, 547 KB)

altmemphy_ext_dll.zip (48 KB)

altmemphy_int_dll.zip (47 KB)

static_dll.zip (18 KB)

• External memory PHY interface (ALTMEMPHY) (nonAFI) megafunction user guide (ver 7.3, Jan 2010, 3 MB)

I/O Interfaces, Protocols and Signal Integrity

• AN 477: Designing RGMII interface with FPGA and HardCopy devices (ver 2.0, Jan 2010, 519 KB)
  
• Input signal edge rate guidance (ver 1.0, Jun 2005, 63 KB)

DSP

• Intel FPGA product catalog (ver 14.0, Jul 2014, 14 MB)

Design Guidelines

• AN 311: ASIC-to-FPGA design methodology and guidelines (ver 3.1, Apr 2009, 286 KB)
  
• AN 477: Designing RGMII interface with FPGA and HardCopy devices (ver 2.0, Jan 2010, 519 KB)
  
• AN 658: Best design practices for HardCopy devices (ver 1.1, Jul 2012, 799 KB)

Development Kits

• Intel FPGA product catalog (ver 14.0, Jul 2014, 14 MB)
  

End Applications

• Intel FPGAs for radar and advanced sensors (ver 1.0, Oct 2007, 219 KB)

General Device Documentation

• Intel FPGAs for radar and advanced sensors (ver 1.0, Oct 2007, 219 KB)
• Generating functionally equivalent FPGAs and ASICs with a single set of RTL and synthesis/timing constraints (ver 1.2, Feb 2009, 459 KB)