Literature: Arria® V Devices

Arria V Device Handbook, Volume 1: Device Interfaces and Integration (ver 2014.07.02, Jul 2014, 3 MB)

Section I. Device Core for Arria V Devices

Section II. I/O Interfaces for Arria V Devices

Section III. System Integration for Arria V Devices

Arria V Device Handbook, Volume 2: Transceivers (ver 2014.09.30, Sep 2014, 3 MB)

Arria V Device Handbook, Volume 3: Hard Processor System Technical Reference Manual (ver 2014.07.31, Jul 2014, 24 MB)

Section I. Overview

Section II. System Interconnect

Section III. Cortex-A9 Microprocessor

Section IV. Debug and Trace

Section V. Memory and Memory Controllers

Section VI. Peripherals

Section VII. Hard Processor System User Guide

Section VIII. Appendices

Section IX. SoC HPS Address Map and Register Definitions

Related Documentation

External Memory Interfaces

Power and Thermal Management

(Final)

PowerPlay early power estimator user guide (1 MB)

(BDTI)

Power delivery network (PDN) tool 2.0 for Stratix® V, Arria V, Arria® II GZ, Cyclone® V, and Cyclone® IV devices (5 MB)

Power delivery network (PDN) tool 2.0 for Intel® Arria® 10 devices (3 MB)

I/O Interfaces, Protocols and Signal Integrity

Intel FPGA JESD204B MegaCore function and ADI AD9250 hardware checkout report (1 MB)

AN 696 reference design example (3 MB)

Arria V GX design files (2 MB)

Stratix V GX design files (1 MB)

an653_reference_design_file (346 KB)

Arria V early SSN estimator (528 KB)

Embedded Memory

DSP

Device Configuration and Remote System Upgrades

user_led.zip (4 KB)

Design Guidelines

(Introspect)

AN 676 reference design example (1 MB)

(BDTI)

PCB Layout and Packaging

(This application note provides guidance on thermal management and mechanical handling of lidless flip chip ball-grid array (FCBGA) for Intel FPGA devices.)

Development Kits

End Applications

(SoftSilicon function)

(SoftSilicon function)

General Device Documentation