A comprehensive static timing analysis includes analysis of register-to-register, I/O, and asynchronous reset paths. The Timing Analyzer uses data required times, data arrival times, and clock arrival times to verify circuit performance and to detect possible timing violations. The Timing Analyzer determines the timing relationships that must be met for the design to correctly function, and checks arrival times against required times to verify timing.
Clock Setup Check
To perform a clock setup check, the Timing Analyzer determines a setup relationship by analyzing each launch and latch edge for each register-to-register path. For each latch edge at the destination register, the Timing Analyzer uses the closest previous clock edge at the source register as the launch edge.
In Figure 1, two setup relationships are defined and labeled Setup A and Setup B. For the latch edge at 10 ns, the closest clock that acts as a launch edge is at 3 ns and is labeled Setup A. For the latch edge at 20 ns, the closest clock that acts as a launch edge is at 19 ns and is labeled Setup B.
The Timing Analyzer reports the result of clock setup checks as slack values. Slack is the margin by which a timing requirement is met or not met. Positive slack indicates the margin by which a requirement is met, and negative slack indicates the margin by which a requirement is not met. The Timing Analyzer determines clock setup slack as shown in Equation 1 for internal register-to-register paths.
Equation 1
Clock Setup Slack = Data Required Time – Data Arrival Time
Data Required = Clock Arrival Time – μtSU – Setup Uncertainty
Clock Arrival Time = Latch Edge + Clock Network Delay to Destination Register
Data Arrival Time = Launch Edge + Clock Network Delay Source Register + μtCO + Register-to-Register Delay
If the data path is from an input port to a internal register, the Timing Analyzer uses the equations shown in Equation 2 to calculate the setup slack time.
Equation 2
Clock Setup Slack Time = Data Required Time – Data Arrival Time
Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + Input Maximum Delay of Pin + Pin to Register Delay
Data Required Time = Latch Edge + Clock Network Delay to Destination Register – μtSU
If the data path is an internal register to an output port, the Timing Analyzer uses the equations shown in Equation 3 to calculate the setup slack time.
Equation 3
Clock Setup Slack Time = Data Required Time – Data Arrival Time
Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + μtCO + Register to Pin Delay
Data Required Time = Latch Edge + Clock Network Delay to Destination Register – Output Maximum Delay of Pin
Clock Hold Check
To perform a clock hold check, the Timing Analyzer analyzer determines a hold relationship for each possible setup relationship that exists for all source and destination register pairs. The Timing Analyzer checks all adjacent clock edges from all setup relationships to determine the hold relationships. The Timing Analyzer analyzer performs two hold checks for each setup relationship. The first hold check determines that the data launched by the current launch edge is not captured by the previous latch edge. The second hold check determines that the data launched by the next launch edge is not captured by the current latch edge.
Figure 2 shows two setup relationships labeled Setup A and Setup B. The first hold check is labeled Hold Check A1 and Hold Check B1 for Setup A and Setup B, respectively. The second hold check is labeled Hold Check A2 and Hold Check B2 for Setup A and Setup B, respectively.
From the possible hold relationships, the Timing Analyzer selects the hold relationship that is the most restrictive. The hold relationship with the smallest difference between the latch and launch edges (that is, latch– launch and not the absolute value of latch – launch) is selected because this determines the minimum allowable delay for the register-to-register path. For Figure 2, the hold relationship selected is Hold Check A2. The Timing Analyzer determines clock hold slack as shown in Equation 4.
Equation 4
Clock Hold Slack = Data Arrival Time – Data Required Time
Data Required Time = Clock Arrival Time +μtH + Hold Uncertainty
Clock Arrival Time = Latch Edge + Clock Network Delay to Destination Register
Data Arrival Time = Launch Edge + Clock Network Delay to Source Register +μtCO+ Register to Register Delay
If the data path is from an input port to an internal register, the Timing Analyzer uses the equations shown in Equation 5 to calculate the hold slack time.
Equation 5
Clock Setup Slack Time = Data Arrival Time – Data Required Time
Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + Input Minimum Delay of Pin + Pin to Register Delay
Data Required Time = Latch Edge + Clock Network Delay to Destination Register + μtH
If the data path is an internal register to an output port, the Timing Analyzer uses the equations shown in Equation 6 to calculate the hold slack time.
Equation 6
Clock Setup Slack Time = Data Arrival Time – Data Required Time
Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + μtCO + Register to Pin Delay
Data Required Time = Latch Edge + Clock Network Delay to Destination Register – Output Minimum Delay of Pin
Recovery and Removal
Recovery time is the minimum length of time an asynchronous control signal, for example, and preset, must be stable before the next active clock edge. The recovery slack time calculation is similar to the clock setup slack time calculation, but it applies asynchronous control signals. If the asynchronous control is registered, the Timing Analyzer uses Equation 7 to calculate the recovery slack time.
Equation 7
Recovery Slack Time = Data Required Time – Data Arrival Time
Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + μtCO+ Register to Register Delay
Data Required Time = Latch Edge + Clock Network Delay to Destination Register – μtSU
If the asynchronous control is not registered, the Timing Analyzer uses the equations shown in Equation 8 to calculate the recovery slack time.
Equation 8
Recovery Slack Time = Data Required Time – Data Arrival Time
Data Arrival Time = Launch Edge + Maximum Input Delay + Port to Register Delay
Data Required Time = Latch Edge + Clock Network Delay to Destination Register Delay – μtSU
Note: If the asynchronous reset signal is from a port (device I/O), you must make an Input Maximum Delay assignment to the asynchronous reset pin for the Timing Analyzer to perform recovery analysis on that path.
Removal time is the minimum length of time an asynchronous control signal must be stable after the active clock edge. The Timing Analyzer removal time slack calculation is similar to the clock hold slack calculation, but it applies asynchronous control signals. If the asynchronous control is registered, the Timing Analyzer uses the equations shown in Equation 9 to calculate the removal slack time.
Equation 9
Removal Slack Time = Data Arrival
Time – Data Required Time
Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + μtCOof Source Register + Register to Register Delay
Data Required Time = Latch Edge + Clock Network Delay to Destination Register + μtH
If the asynchronous control is not registered, the Timing Analyzer uses the equations shown in Equation 10 to calculate the removal slack time.
Equation 10
Removal Slack Time = Data Arrival Time – Data Required Time
Data Arrival Time = Launch Edge + Input Minimum Delay of Pin + Minimum Pin to Register Delay
Data Required Time = Latch Edge + Clock Network Delay to Destination Register +μtH
Note: If the asynchronous reset signal is from a device pin, you must specify the Input Minimum Delay constraint to the asynchronous reset pin for the Timing Analyzer to perform a removal analysis on this path.
Multicycle Paths
Multicycle paths are data paths that require more than one clock cycle to latch data at the destination register. For example, a register may be required to capture data on every second or third rising clock edge.
Figure 3 shows an example of a multicycle path between a multiplier’s input registers and output register where the destination latches data on every other clock edge. Refer to Timing Analyzer set_multicycle_path Command for information about the set_multicycle_path command.
The following pages provide information about SDC commands for describing clocks and clock characteristics.