There are two forms of clock latency: source and network. Source latency is the propagation delay from the origin of the clock to the clock definition point (for example, a clock port), and network latency is the propagation delay from a clock definition point to a register’s clock pin. The total latency (or clock propagation delay) at a register’s clock pin is the sum of the source and network latencies in the clock path.
You can use the set_clock_latency command to specify input delay constraints to ports in the design. The following list shows the set_clock_latency command including the available options:
set_clock_latency -source [-rise | -fall] [-late | -early] <delay> <object list>
Table 1 describes the options for the set_clock_latency command.
|-source||Specify a source latency.|
|-rise | -fall||Specify the rising or falling delays.|
|-late | -early||Specifies the earliest or the latest arrival times to the clock.|
|<delay>||Specifies the delay value.|
|<object list>||Specifies the clocks or clock sources if a clock is clocked by more than one clock.|
The Timing Analyzer automatically computes network latencies, therefore, the set_clock_latency command specifies only the source latencies.