VHDL: Unsigned Multiplier with Registered I/O

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This example describes an 8-bit unsigned multiplier design with registered I/O in VHDL.

Figure 1. Unsigned multiplier top-level diagram.

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Table 1. Unsigned Multiplier Port Listing

Port Name Type Description
a[7:0],
b[7:0]
Input 8-bit unsigned, registered data inputs. Input data is fed into the multiplier at each clock cycle
clk Input Clock input
clear Input Asynchronous clear input
result[15:0] Output 16-bit registered data output