VHDL: Unsigned Multiplier with Registered I/O



This example describes an 8-bit unsigned multiplier design with registered I/O in VHDL.

Figure 1. Unsigned multiplier top-level diagram.

Download the files used in this example:

The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.

Table 1. Unsigned Multiplier Port Listing

Port Name Type Description
Input 8-bit unsigned, registered data inputs. Input data is fed into the multiplier at each clock cycle
clk Input Clock input
clear Input Asynchronous clear input
result[15:0] Output 16-bit registered data output