The FPGA-to-HPS bridges design example exercises the memory mapped interfaces of the hard processor system (HPS) exposed to the FPGA fabric. The design performs memory tests by writing and reading the HPS memory using various ports of the HPS and measures the performance of the data movements.
The design is provided for the following development kits:
The design is compiled using the following tools:
- Intel® Quartus® Prime software v16.0
- Intel® SoC FPGA Embedded Design Suite (EDS) v16.0
The design uses a pair of modular SGDMAs and a pseudorandom binary sequence (PRBS) pattern checker and generator to move data between the FPGA fabric and the HPS SDRAM controller and tests the integrity of the data. The design exercises the FPGA-to-HPS bridge to perform cacheable and non-cacheable accesses to SDRAM. The design also exercises the FPGA-to-SDRAM interfaces, which allow the FPGA to access the HPS SDRAM directly without passing data through the HPS L3 interconnect or memory protection unit (MPU) accelerator coherency port.
Hardware Design Specifications
- Arria® 10 HPS
- 1GB of DDR4-SDRAM
- Direct memory access (DMA) subsystem
- PRBS Pattern Checker (custom intellectual property (IP) provided with this design)
- PRBS Pattern Generator (custom IP provided with this design)
Using This Design Example
Download the Cyclone V FPGA-to-HPS Bridges design example readme (.txt file)
The use of this design is governed by, and subject to, the terms and conditions of the Hardware Reference Design License Agreement.
The .zip file contains all the necessary hardware and software files to reproduce the example, as well as a readme.txt file. The readme.txt file contains instructions for re-building the design.