Passive Parallel Asynchronous Configuration

During PPA configuration, data is transferred from a configuration device, flash memory, or other storage device to the Intel® FPGA device on the DATA[7..0] pins. This configuration scheme is asynchronous, so control signals regulate the configuration cycle.

For more information, please refer to the configuration chapter of the relevant Intel® FPGA device in the Configuration Handbook.

Configuration Method

• Using an intelligent host such as microprocessor or CPLD

Reference Design

• MAX® series configuration controller using flash memory white paper (PDF) ›
• Using a MAX® or MAX® II CPLD as a configuration controller to configure Intel® FPGAs from flash memory
• Source Code (ZIP) in Verilog and VHDL