Article ID: 000099598 Content Type: Troubleshooting Last Reviewed: 08/30/2024

​​​​​​​Why does rx_ready[i](i>0) of F-tile PMA/FEC Direct PHY FPGA IP tie to 0 when the number of PMA lanes is set to more than one and enabled per PMA lanes TX and RX ready signal?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, rx_ready[i](i>0) of F-Tile PMA/FEC Direct PHY FPGA IP tie to 0 when the number of PMA lanes set to more than one and enable per PMA lanes TX and RX ready signal.

     

     

    Resolution

    To work around this problem in the Quartus® Prime Pro Edition software version 24.1, can monitor rx_lane_current_state[i][1] to instead rx_ready[i](i>0) status.

    This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software.
     

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs

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