Description
When using some optic modules, you may see uncorrectable FEC errors or ‘o_rx_pcs_ready’ signal low during reset testing for F-Tile Ethernet Intel FPGA Hard IP variant for PAM4 links with FEC enabled.
Resolution
The workaround for this problem is to understand the link settling time for the module and increase the delay before checking the link. You may need to issue another reset to recover the link.