Why does the F-tile Serial Lite IV Intel® FPGA IP design with PAM4 modulation fail achieving link up during simulation?

Due to a problem in the Quartus® Prime Pro Edition software 24.2 and earlier versions, you might observe the F-tile Serial Lite IV Intel FPGA IP design with PAM4 modulation fail to get rx_link_up asserted in simulation. This is because rx_cdr_lock is not asserted, incurs rx_pcs_ready not assert. This failure is caused by misinterpreting AIB master and slave, introducing a deskew error in serial data in the soft reset controller.

There is no workaround available.

• This problem only exists in simulation and does not impact the hardware testing results.
• This problem might disappear when you re-run the simulation. This is because the simulator might support random seed generation, and some seeds will not encounter this failure.

This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software.